Documentation
DSPI_FIFO-Ava

Serial Peripheral Interface – Master/Slave with FIFO and Avalon interface


The DSPI_FIFO-Avalon is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. The DSPI_FIFO-Avalon uses Avalon bus on the parallel interface side. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. The DSPI_FIFO-Avalon data are simultaneously transmitted and received. The DSPI_FIFO-Avalon is a technology independent design that can be implemented in a variety of process technologies. The DSPI_FIFO-Avalon system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
The DSPI_FIFO-Avalon automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI_FIFO-Avalon output drivers if more than one SPI devices simultaneously attempts to become bus master.
The DSPI_FIFO-Avalon supports two DMA modes: single transfer and multi-transfer. These modes allow DSPI_FIFO-Avalon to inter-face to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
The DSPI_FIFO-Avalon is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The DSPI_FIFO-Avalon is a technology independent design that can be implemented in a variety of process technologies.

Key Features

Applications

  • Compliant with Avalon interface specification, Revision 1.0
  • SPI Master
    • Master and Multi-master operations
    • Two modes of operation: SPI mode and FIFO mode
    • 8 SPI slave select lines
    • System error detection
    • Mode fault error
    • Write collision error
    • Interrupt generation
    • Supports speeds up ¼ of system clock
    • Bit rates generated 1/4 - 1/512 of system clock.
    • Four transfer formats supported
  • SPI Slave
    • Slave operation
    • Two modes of operation: SPI mode and FIFO mode
    • System error detection
    • Interrupt generation
    • Supports speeds up ¼ of system clock
    • Four transfer formats supported
  • Fully synthesizable
  • Two DMA Modes allows single and multi-transfer
  • In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU
  • Optional FIFO size extension to 128, 256 or 512 Bytes
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Digital multimeters

Symbol

 clk
 reset
rxrdy 
txrdy 
 mi
 si
mo 
so 
 writedata (7:0)
 write
 read
 chipselect
readdata (7:0) 
 scki
scko 
 ss
scken 
sso (7:0) 
irq 
soen 

Pins description

PinTypeDescription
clkinputGlobal clock
resetinputGlobal reset
miinputMaster serial data input
siinputSlave serial data input
writedata (7:0)inputAvalon write data bus
writeinputAvalon write control
readinputAvalon read data bus
chipselectinputAvalon chip select
sckiinputSPI clock input
ssinputSlave Select
rxrdyoutputReceiver ready output
txrdyoutputTransmitter ready output
mooutputMaster serial data output
sooutputSlave serial data output
readdata (7:0)outputAvalon read data bus
sckooutputSPI clock output
sckenoutputSPI clock output enable
sso (7:0)outputSlave select outputs
irqoutputInterrupt request
soenoutputSlave output enable

Block diagram

RX FIFO
DMA Controller
rxrdy
txrdy
Shift register
mi
mo
si
so
TX FIFO
Avalon Interface
writedata (7:0)
readdata (7:0)
write
read
chipselect
SPI Clock Logic
scki
scko
SPI Controller
scken
ss
sso (7:0)
irq
soen
clk
reset

Units

RX FIFO

The Rx FIFO can be 64 (128, 256, 512) levels deep, it receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time if interrupt is enabled, the DSPI_FIFO will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it is full, and will not accept any next byte. Any more data entering the Rx shift register will set the Over-run Error flag.

DMA Controller

TXRDY, RXRDY - Transmitter and Receiver DMA signaling are available through this two pins. When operating in the FIFO mode, one of two types of DMA signaling per pin can be selected via SFCR3. When operating as in the SPI Mode, only DMA mode 0 is allowed. Mode 0 supports single transfer DMA where a transfer is made between CPU bus cycles. Mode 1 supports multi-transfer DMA where multiple transfers are made continuously until the RCVR FIFO has been emptied or the XMIT FIFO has been filled.

Shift register

It is a central element in the SPI system. The system is single buffered in the transmit direction and double buffered in the receive direction. This fact means new data for transmission cannot be written to the shifter until the previous transaction is complete; however, received data is transferred into a parallel read data buffer so the shifter is free to accept a second serial character. As long as the first character is read out of the read data buffer before the next serial character is ready to be transferred, no overrun condition will occur. When an SPI transfer occurs, an 8-bit character is shifted out on data pin while a different 8-bit character is simultaneously shifted in a second data pin. Another way to view this transfer is that an 8-bit shift register in the master and another 8-bit shift register in the slave are connected as a circular 16-bit shift register. When a transfer occurs, this distributed shift register is shifted eight bit positions; thus, the characters in the master and slave are effectively exchanged.

TX FIFO

The Tx portion of the DSPI_FIFO transmits data through SO/MO as soon as the CPU loads a byte into the Tx FIFO in Master mode. In Slave mode the transmission is started after correct edge of the SCK signal. The DSPI_FIFO will prevent loads to the Tx FIFO if it currently holds 64 (128, 256, 512) characters (depending on SFCR(5) bit value and selected FIFO size). Loading to the Tx FIFO again will be enabled as soon as the next character is transferred to the Tx shift register. These capabilities ac-count for the largely autonomous operation of the Tx

Avalon Interface

Avalon Interface performs the interface functions between DSPI_FIFO internal blocks and Avalon bus. Allows easy connection of the core to existing Avalon systems.

SPI Clock Logic

Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock and has no significant effect on the transfer format. The clock phase (CPHA) control bit selects one of two fundamentally different transfer formats. The clock phase and polarity should be identical for the master SPI device and the communicating slave device. In some cases, the phase and polarity are changed between transfers to allow a master device to communicate with peripheral slaves having different requirements. The flexibility of the SPI system on the DSPI allows direct interface to almost any existing synchronous serial peripheral.

SPI Controller

SPI Controller manages the Master/Slave operation and controls the transmission. The SPI Controller manages the transmission speed and format (Phase and polarity). Controller is also responsible for generating of interrupt request and detection of transmission errors.