Programmable Timer Module
The D6840 is a programmable timer module compatible with 6840 industry standard. This IP core is designed for using as peripheral device for D68xx processors or as separate module in applications where features of 6840 timer are useful. The D6840 has three separate 16-bit timers, with separate control and common status registers. The timers may be used for square wave generation with duty cycle regulation. Signal may be generated as continuous wave or single-shot mode. There is also capability for using D6840 module for frequency or pulse width measurement and comparison. The D6840 has interrupt which is useful in controlling module by CPU.
The D6840 is a technology independent design that can be implemented in a variety of process technologies.
Figure below shows typical connection of the D6840 to microcontroller.

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- Compatible with 6840 industry standard
- Three separate timers
- Two operation modes
- Wave synthesis
- Wave measurement
- Two generation modes
- Gating system for each clock input
- Separate timer outputs
- Prescaler mode for timer3 input clock
- External clock or E clock used for timer decrement
- Interrupt generation
- Split bus for input and output data
- Fully synthesizable
- Static synchronous design and no internal tri-states
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- External module for D68xx processors
- Gated wave generation
- Pulse width modulation
- Frequency measurement and comparison
- Pulse width measurement and comparison
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 g3
o3 
 c3
 datai (7:0)
 rs (2:0)
 rw
 cs0
 cs1
irq 
datao (7:0) 

| Pin | Type | Description |
| e | input | E clock input |
| reset | input | Global reset |
| clk | input | Global clock |
| g3 | input | Timer 3 clock gate input |
| c3 | input | Timer 3 external clock input |
| datai (7:0) | input | Data bus input |
| rs (2:0) | input | Register select |
| rw | input | Read/write control |
| cs0 | input | Chip select 0 |
| cs1 | input | Chip select 1 |
| c1 | input | Timer 1 external clock input |
| g1 | input | Timer 1 clock gate input |
| c2 | input | Timer 2 external clock input |
| g2 | input | Timer 2 clock gate input |
| o3 | output | Timer 3 output |
| irq | output | Interrupt request |
| datao (7:0) | output | Data bus output |
| o1 | output | Timer 1 output |
| o2 | output | Timer 2 output |

g3 
o3 
c3 
 irq
 datai (7:0)
 datao (7:0)
 rs (2:0)
 rw
 cs0
 cs1

Timer 3Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt
C3 prescallerClock divider for C3 input. Used for divide clock by 8 in prescaled mode of timer3
CPU interfacePerforms access to internal registers from CPU. This module contains all control and status registers. There is also MSB and LSB buffer used for access to 16-bit counter and Latch.
Timer 1Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt
Timer 2Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation | Speed grade | Utilized Area [LC] | Frequency [MHz] |
| CYCLONE | -6 | 501 | 173 |
| CYCLONE-II | -6 | 498 | 213 |
| CYCLONE-III | -6 | 502 | 224 |
| STRATIX | -5 | 501 | 168 |
| STRATIX-II | -3 | 333 | 281 |
| STRATIX-III | -3 | 330 | 384 |
D6840 implementation results for ALTERA devices. All features have been included.
| Implementation | Speed grade | Utilized Area [Slices] | Frequency [MHz] |
| SPARTAN-II | -6 | 305 | 100 |
| SPARTAN-IIE | -7 | 318 | 112 |
| SPARTAN-III | -5 | 311 | 145 |
| SPARTAN-IIIE | -5 | 328 | 166 |
| VIRTEX | -6 | 341 | 95 |
| VIRTEX-E | -8 | 318 | 111 |
| VIRTEX-II | -6 | 254 | 172 |
| VIRTEX-IV | -12 | 315 | 252 |
| VIRTEX-V | -3 | 173 | 346 |
D6840 implementation results for XILINX devices. All features have been included.
| Implementation | Speed grade | Utilized Area [LUT/PFU] | Frequency [MHz] |
| SC | -7 | 495/173 | 262 |
| ECP2 | -7 | 448/192 | 214 |
| XP2 | -7 | 448/192 | 145 |
| XP | -5 | 433/192 | 130 |
| ECP | -5 | 433/192 | 161 |
| EC | -5 | 433/192 | 161 |
D6840 implementation results for LATTICE devices. All features have been included.
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