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 Datasheet 
D6840

Programmable Timer Module


The D6840 is a programmable timer module compatible with 6840 industry standard. This IP core is designed for using as peripheral device for D68xx processors or as separate module in applications where features of 6840 timer are useful. The D6840 has three separate 16-bit timers, with separate control and common status registers. The timers may be used for square wave generation with duty cycle regulation. Signal may be generated as continuous wave or single-shot mode. There is also capability for using D6840 module for frequency or pulse width measurement and comparison. The D6840 has interrupt which is useful in controlling module by CPU.
The D6840 is a technology independent design that can be implemented in a variety of process technologies.

Figure below shows typical connection of the D6840 to microcontroller.





Key Features

Applications

  • Compatible with 6840 industry standard
  • Three separate timers
  • Two operation modes
    • Wave synthesis
    • Wave measurement
  • Two generation modes
    • Continuous
    • Single shot
  • Gating system for each clock input
  • Separate timer outputs
  • Prescaler mode for timer3 input clock
  • External clock or E clock used for timer decrement
  • Interrupt generation
  • Split bus for input and output data
  • Fully synthesizable
  • Static synchronous design and no internal tri-states
  • External module for D68xx processors
  • Gated wave generation
  • Pulse width modulation
  • Frequency measurement and comparison
  • Pulse width measurement and comparison



Symbol

 e
 reset
 clk
 g3
o3 
 c3
 datai (7:0)
 rs (2:0)
 rw
 cs0
 cs1
irq 
datao (7:0) 
 c1
 g1
o1 
 c2
 g2
o2 

Pins description

PinTypeDescription
einputE clock input
resetinputGlobal reset
clkinputGlobal clock
g3inputTimer 3 clock gate input
c3inputTimer 3 external clock input
datai (7:0)inputData bus input
rs (2:0)inputRegister select
rwinputRead/write control
cs0inputChip select 0
cs1inputChip select 1
c1inputTimer 1 external clock input
g1inputTimer 1 clock gate input
c2inputTimer 2 external clock input
g2inputTimer 2 clock gate input
o3outputTimer 3 output
irqoutputInterrupt request
datao (7:0)outputData bus output
o1outputTimer 1 output
o2outputTimer 2 output

Block diagram

Timer 3
g3
o3
C3 prescaller
c3
CPU interface
irq
datai (7:0)
datao (7:0)
rs (2:0)
rw
cs0
cs1
Timer 1
c1
g1
o1
Timer 2
c2
g2
o2
e
reset
clk

Units

Timer 3

Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt

C3 prescaller

Clock divider for C3 input. Used for divide clock by 8 in prescaled mode of timer3

CPU interface

Performs access to internal registers from CPU. This module contains all control and status registers. There is also MSB and LSB buffer used for access to 16-bit counter and Latch.

Timer 1

Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt

Timer 2

Module, which contains 16-bit counter with all logic used for decrement, gating input clock and generating output signal and interrupt

Performance


Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

ImplementationSpeed
grade
Utilized Area
[LC]
Frequency
[MHz]
CYCLONE-6501173
CYCLONE-II-6498213
CYCLONE-III-6502224
STRATIX-5501168
STRATIX-II-3333281
STRATIX-III-3330384

D6840 implementation results for ALTERA devices. All features have been included.

ImplementationSpeed
grade
Utilized Area
[Slices]
Frequency
[MHz]
SPARTAN-II-6305100
SPARTAN-IIE-7318112
SPARTAN-III-5311145
SPARTAN-IIIE-5328166
VIRTEX-634195
VIRTEX-E-8318111
VIRTEX-II-6254172
VIRTEX-IV-12315252
VIRTEX-V-3173346

D6840 implementation results for XILINX devices. All features have been included.

ImplementationSpeed
grade
Utilized Area
[LUT/PFU]
Frequency
[MHz]
SC-7495/173262
ECP2-7448/192214
XP2-7448/192145
XP-5433/192130
ECP-5433/192161
EC-5433/192161

D6840 implementation results for LATTICE devices. All features have been included.