LCD/TFT Display Controller

The DLCD is display controller with 24-bit RGB output and synchronization. It may be used for displaying data on LCD as well as CRT displays. Pixel data has 8-bit resolution and 24-bit RGB output is generated using external LUT with defined color palette. The DLCD is controlled by CPU and uses external data memory for display data. All parameters are configurable through CPU register interface. The core is designed to use with DCD's DP80xxx series of MCU.
The display controller is perfect for MCU based applications where static graphic data are displayed using LCD/TFT matrix or CRT monitor.
The DLCD is a technology independent design that can be implemented in a variety of process technologies.

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Maximum resolution 1024 x 1024 pixels 24-bit RGB output, 8-bit pixel with external LUT for color palette Configurable screen parameters Configurable memory data bus width Wait states for memory access Pixel clock divider Display data copying without CPU access Display data accessible for CPU as external data memory Fully synthesizable Static synchronous design and no internal tri-states		Microcontroller based application Displaying data on LCD/TFT matrix Displaying data on LCD/TFT or CRT monitor

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
xdatai (7:0)	input	CPU interface, external data memory input bus
xrd	input	CPU interface, external data memory read control
xwr	input	CPU interface, external data memory write control
xcs	input	CPU interface, external data memory chip select
mdatai (31:0)	input	Memory data input bus
xaddr (19:0)	input	CPU interface, external data memory address input
cdatai (23:0)	input	Color palette LUT data bus
datai (7:0)	input	Register data input
addr (3:0)	input	Register address bus
rd	input	Register read control
wr	input	Register write control
cs	input	Register access chip select
pclken	output	Divided pixel clock output enable
pclkdivo	output	Divided pixel clock output
xdatao (7:0)	output	CPU interface, external data memory output bus
mdatao (31:0)	output	Memory data output bus
mrd	output	Memory read control
mwr	output	Memory write control
mcs	output	Memory chip select
maddr (18:0)	output	Memory address bus
byteen (3:0)	output	Byte enable for memory data bus
ready	output	Ready control
caddr (7:0)	output	Color palette LUT address bus
r (7:0)	output	Red color data output
g (7:0)	output	Green color data output
b (7:0)	output	Blue color data output
hsync	output	Horizontal sync
vsync	output	Vertical sync
de	output	Data enable for display
irq	output	Interrupt request
datao (7:0)	output	Register data output