8-bit Fast Microcontroller

The DF6803 is synthesisable SOFT Microcontroller IP Core fully software compatible to the Motorola MC6803. The DF6803 has enhanced internal architecture, which allows it to execute the code ca. 4 times faster than original 6803 running at the same clock frequency.

The DF6803 has built in real time hardware on chip debugger the DoCD^TM, allowing easy software debugging and validation.
The DF6803 is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.




Each of the DCD's D6803 Core has built in support for DCD Hardware Debug System called DoCD^TM. It is a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

---

Improved, 4 times faster architecture Software compatible with industry standard MC6803 I/O Wrapper making it pin compatiblecore Power saving mode: WAI Fully synthesizable Static synchronous design No internal tri-states Scan test ready One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode Memory Expansion Unit and Chip Selects Floating Point Coprocessor MDU - Multiply Divide Unit

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface Three 8-bit and one 5-bit I/O Ports Extended Interrupt Controller Programmable three function 16-bit timer/counter system 16 bit free running counter Compare/Capture functions Timer clocked by internal source Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise,Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART Three SCI Related interrupts

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
cmf	input	Clock monitor fail reset
halt	input	Halt clock system
irq	input	Interrupt input
nmi	input	Non-maskable interrupt input
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
iramdatai (7:0)	input	Internal Data memory bus input
xdatai (7:0)	input	External memory bus input
port1 (7:0)	output	Bidirectional Port 1
port2 (4:0)	output	Bidirectional Port 2, shared with SCI and programmable timer devices
port3 (7:0)	output	Bidirectional Port 3, shared with Low address Byte and Data bus. (Demultiplexed Address/Data bus is also possible)
port4 (7:0)	output	Bidirectional Port 4, shared with high address byte in Expanded mode
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line
iramoe	output	Internal Program / Data memory output enable
iramwe	output	Internal Program / Data memory write enable
xwe	output	External memory write enable
xoe	output	External memory output enable
addr (15:0)	output	Common address bus
datao (7:0)	output	Data bus output