SDRAM Controller

The DSDRAM is a soft Core of configur-able SDRAM controller. It is fully compliant to the JEDEC PC100/133 standards. DSDRAM can operate with any SDRAM memory device in terms of size, and required timing parame-ters. All access timing parameters such as CAS latency, refresh interval, etc., are pro-grammable to support different speed grades of SDRAM devices and different operating frequencies. The timing parameters can be set to the proper default values during syn-thesis time. It is very small, efficient, static fully syn-chronous design with no internal tri-state buffers and signals.

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Supports any SDRAM discrete devices PC 66/100/133 SDRAM SDRAM from 16 Mbit to 1024 Mbit sizes Programmable data size 8, 16, and 32 bits Supports all burst lengths 1, 2, 4, 8 and full page CAS latency 1, 2, and 3 Programmable access timing parameters Supports multiple external SDRAM banks Automatic refresh generation with programmable refresh intervals Self refreshing mode Fully synthesizable, static design with no internal tri-states

Pin	Type	Description
rst	input	Global reset
clk	input	Global clock
address (23:0)	input	Processor address bus
datai (31:0)	input	Data Bus input
cs	input	Chip select
wr	input	Processor data write
rd	input	Processor data read
be (2:0)	input	Byte enable
sddq (31:0)	output	SDRAM databus
datao (31:0)	output	Processor data bus output
busy	output	Processor data busy