Serial EEPROM Controller

The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. The serial EEPROM contents is accessible to CPU in the same manner as common SRAM memory, but requires READY input to expand time access. The core allows to map serial EEPROM in processor memory space, and control it as the parallel memory. The controller automatically sends all the EEPROM control instructions and read, write memory locations. For the processor the EEPROM connected to processors through the DEEPROM is visible and controlled as parallel SRAM with long access time. The Core is designed to operate with popular 25XXX SPI Serial EEPROMs (Atmel, Microchip).

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Standard memory interface with ready control Configurable SPI parameters Serial clock prescaler SPI mode CS hold/setup Updating bits in EEPROM status register Simple interface allows easy connection to microcontrollers Fully synthesizable, static design with no internal tri-states		Applcations requiring data storage in external non-voltile memories

Pin	Type	Description
rst	input	Global reset
clk	input	Global clock
addr (15:0)	input	Micrcprocessor address bus
datai (7:0)	input	Data Bus input
wr	input	Write signal
rd	input	Read input
cs	input	Chip select
esi	input	EEPROM serial data input
datao (7:0)	output	Databus output
ready	output	Ready signal
eso	output	Serial data output
eck	output	Serial clock
ecs	output	EEPROM Chip Select