Forward Discrete Cosine Transform

The DFDCT core implements 8-point 2D Forward Discrete Cosine Transform. The DFDCT is high performance and area optimized module designed for reuse in wide range of ASIC and FPGA technologies. It can be used in any multimedia and digital video applications.

The Forward Discrete Cosine Transform (FDCT) is a transformation method that converts the block of input samples from spatial domain to its constituent frequency components as represented by a set of coefficients. For an image the FDCT is performed on 2-D array of samples, resulting in a 2-D array of frequency coefficients. The lower frequency coefficients appear toward the upper left-hand corner of the FDCT matrix, and the higher frequency coefficients are in the lower right-hand corner of the FDCT matrix. The DFDCT core can perform Forward Discrete Cosine Transform on an 8x8 block of samples. The algorithm used for the calculation is based on the following equation:




The DFDCT core uses the row/column algorithm where transformation is implemented as two separate one dimensional (1-D) processes.

Connection to Transpose Memory

DFDCT Block Diagram

---

8x8 DCT block size Low latency (77 clock cycles) Continuous operation (one clock cycle per sample) Supports signed and unsigned input data format (zero-level shifting) Configuration parameters : Input data bus width Output data bus width Cosine coefficients width Transpose memory bus width Internal precision Synthesizable static synchronous design No internal tri-states Scan test ready	JPEG image compression standard MPEG1 digital video standard MPEG2 digital video standard MPEG4 digital video standard H.261 video conferencing standard H.263 video conferencing standard

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
datai (7:0)	input	Data bus for DCT input samples.
start	input	Indicates that the first sample of the block is available for processing.
ramdatai (15:0)	input	Data bus from transpose memory.
datao (7:0)	output	Data bus for DCT output coefficients.
busy	output	Indicates that DCT core can process new block of data
ready	output	Indicates that DCT output coefficients are available on datao bus.
sob	output	Start Of Block output. Signalizes that the first element (DC coefficient) of the output block is available on the datao bus.
wrramaddr (5:0)	output	Transpose memory write address
rdramaddr (5:0)	output	Transpose memory read address
ramdatao (15:0)	output	Data bus for transpose memory
ramwe	output	Transpose memory write enable
ramoe	output	Transpose memory output enable