8-bit Microcontroller

The D68HC05 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. The D68HC05 soft core is binary and cycle - compatible with the industry standard Motorola 68HC05 8-bit microcontroller. The Core in standard configuration has integrated on chip major peripheral functions. The D68HC05 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI), and can also be equipped with the Synchronous Serial Peripheral Interface (SPI). The main 16-bit, free-running timer system has two input capture lines, and two output-compare lines. Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the D68HC05 IP Core especially attractive for automotive and battery-driven applications.
D68HC05 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.


Each DCD's D68XX Core has built in support for DCD Hardware Debug System called DoCD^TM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

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Standard architecture, cycle compatible with original implementation Software compatible with industry standard 68HC05 Up to 64K bytes of Data Memory Up to 64K bytes of Code Memory Pin to pin compatibility with 68HC05 devices Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories. Fully synthesizable Static synchronous design No internal reset generator or gated clock Positive edge clocking and no internal tri-states Scan test ready One global system clock Synchronous reset All asynchronous input signals are synchronized before internal use Synchronous logic without microcode The D68HC05 Microcontroller Core has built in hardware on chip debugger DoCDTM which can be easily switched on/of by changing single parameter in the core package. This configurability allows user to have the DoCDTM "on board" at the prototyping level, and then switch it off in mass production. This feature allows to save space in silicon in production items. DoCDTM debug unit used unused Also peripheral components are configurable the same way as DoCDTM. Besides mentioned above parameter all available peripherals can be excluded from the core by changing appropriate constants in package file.

DoCDTM debug unit Processor execution control Read-write all processor contents Hardware execution breakpoints Three wire communication interface I/O Ports Extended Interrupt Controller 7 interrupt sources 7 priority levels Main16-bit timer/counter system 16 bit free running counter Timer clocked by internal source 16-bit Compare/Capture Unit Two independent input-capture functions Two output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator Pulse width modulation Pulse width measuring Full-duplex UART - SCI Standard Non-return to Zero format (NRZ) 8 or 9 bit data transfer Integrated BAUD Rate generator Enhanced receiver data sampling technique Noise, Overrun and Framing errors detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE Three SCI Related interrupts

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
irq	input	External interrupt request input
tcap	input	Timer Capture channel input
docddatai	input	DoCDTM serial data input
clkdocd	input	Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped).
halt	output	Halt clock system during STOP Instruction
tcmp	output	Timer compare channel output
docddatao	output	DoCDTM serial data output
docdclk	output	DoCDTM serial data clock line
port A (7:0)	output	Bidirectional general purpose I/O port
port B (7:0)	output	General Purpose I/O Port
port C (7:0)	output	General purpose I/O Port
port D (7:0)	output	8-bit port shared with SPI and SCI interfaces