Serial Peripheral Interface – Master/Slave with FIFO and APB interface

The DSPI_FIFO-APB is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. The DSPI_FIFO-APB uses APB bus on the parallel interface side. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. The DSPI_FIFO-APB data are simultaneously transmitted and received. The DSPI_FIFO-APB is a technology independent design that can be implemented in a variety of process technologies. The DSPI_FIFO-APB system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of eight different bit rates for the serial clock.
The DSPI_FIFO-APB automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O), and address SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communications. A writecollision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI_FIFO-APB output drivers if more than one SPI devices simultaneously attempts to become bus master.
The DSPI_FIFO-APB supports two DMA modes: single transfer and multi-transfer. These modes allow DSPI_FIFO-APB to inter-face to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
The DSPI_FIFO-APB is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The DSPI_FIFO-APB is a technology independent design that can be implemented in a variety of process technologies.

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Compliant with AMBA specification, Revision 2.0 SPI Master Master and Multi-master operations Two modes of operation: SPI mode and FIFO mode 8 SPI slave select lines System error detection Mode fault error Write collision error Interrupt generation Supports speeds up ¼ of system clock Bit rates generated 1/4 - 1/512 of system clock. Four transfer formats supported SPI Slave Slave operation Two modes of operation: SPI mode and FIFO mode System error detection Interrupt generation Supports speeds up ¼ of system clock Four transfer formats supported Fully synthesizable Two DMA Modes allows single and multi-transfer In the FIFO mode transmitter and receiver are each buffered with 16/64 byte FIFO's to reduce the number of interrupts pre-sented to the CPU Optional FIFO size extension to 128, 256 or 512 Bytes Static synchronous design Positive edge clocking and no internal tri-states Scan test ready

Embedded microprocessor boards Consumer and professional audio/video Home and automotive radio Low-power applications Communication systems Digital multimeters

Pin	Type	Description
presetn	input	Active low APB global reset
pclk	input	APB global clock
mi	input	Master serial data input
si	input	Slave serial data input
pwdata (7:0)	input	APB write data bus
pwrite	input	APB write strobe
penable	input	Indicates the second cycle of APB transfer
psel	input	APB slave select
paddr (2:0)	input	APB address bus
scki	input	SPI clock input
ss	input	Slave select
mo	output	Master serial data output
so	output	Slave serial data output
rxrdy	output	Receiver ready output
txrdy	output	Transmitter ready output
prdata (7:0)	output	APB read data bus
scko	output	SPI clock output
scken	output	SPI clock output enable
sso (7:0)	output	Slave select outputs
int	output	Interrupt request
soen	output	Slave output enable