Configurable UART with APB interface

The D16450-APB is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C450. The D16450-APB performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the parallel bus. The D16450-APB provides APB interface on parallel side of the core. Device connected through APB interface can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). The D16450-APB includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (2¹⁶-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16450-APB has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
The D16450-APB includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
The D16450-APB is a technology independent design that can be implemented in a variety of process technologies.

The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the PCLK frequency.

The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16450-APB core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

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Compliant with AMBA specification, Revision 2.0 Software compatible with 16450 UART Configuration capability Separate configurable BAUD clock line Majority Voting Logic Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data Independently controlled transmit, receive, line status, and data set interrupts False start bit detection 16 bit programmable baud generator Independent receiver clock input MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD) Fully programmable serial-interface characteristics: 5-, 6-, 7-, or 8-bit characters Even, odd, or no-parity bit generation and detection 1-, 1½-, or 2-stop bit generation Internal baud generator Complete status reporting capabilities Line break generation and detection. Internal diagnostic capabilities: Loop-back controls for communications link fault isolation Break, parity, overrun, framing error simulation Full prioritized interrupt system controls Fully synthesizable Static synchronous design and no internal tri-states		Serial Data communications applications Modem interface Embedded microprocessor boards The following parameters of the D16450-APB core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. Baud generator enable disable External RCLK source enable disable External BAUDCLK source enable disable Asynchronous input buffer enable disable Modem Control enable disable SCR register enable disable

Pin	Type	Description
presetn	input	Active low APB global reset
pclk	input	APB global clock
pwdata (7:0)	input	APB write data bus
pwrite	input	APB write strobe
penable	input	Indicates the second cycle of APB transfer
psel	input	APB slave select
paddr (2:0)	input	APB address bus
rclk	input	Receiver clock
si	input	Serial data input
baudclken	input	Baud generator clock enable
baudclk	input	Baud generator clock
prdata (7:0)	output	APB read data bus
so	output	Serial data output
intr	output	Interrupt request output
baudout	output	Baud generator output