Documentation
Application Notes Products Summary
DI2CS-Ava

I2C Bus Interface - Slave with Avalon interface



The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CS-Avalon core provides an interface between parallel Avalon bus and serial I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The DI2CS-Avalon core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS-Avalon supports all the transmission speed modes.
The DI2CS-Avalon is a technology independent design that can be implemented in a variety of process technologies.


Key Features

Applications

  • Compliant with Avalon interface specification, Revision 1.0
  • Single Avalon input clock for registers and I2C bus serial clock generation
  • Conforms to v.3.0 of the I2C specification
  • Slave operation
    • Slave transmitter
    • Slave receiver
  • Supports 3 transmission speed modes
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
  • Allows operation from a wide range of input clock frequencies
  • Simple interface allows easy connection to existing Avalon systems
  • Interrupt generation
  • User-defined data setup time
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Embedded microprocessor boards
  • Consumer and professional audio/video
  • Home and automotive radio
  • Low-power applications
  • Communication systems
  • Cost-effective reliable automotive systems


Symbol

 clk
 reset
irq 
 sdai
sdao 
 scli
sclo 
 writedata (7:0)
 write
 read
 chipselect
readdata (7:0) 

Pins description

PinTypeDescription
clkinputGlobal clock
resetinputGlobal reset
sdaiinputI2C bus data line (input)
scliinputI2C bus clock line (input)
writedata (7:0)inputAvalon write data bus
writeinputAvalon write data bus
readinputAvalon read data bus
chipselectinputAvalon chip select
irqoutputInterrupt request
sdaooutputI2C bus data line (output)
sclooutputI2C bus clock line (output)
readdata (7:0)outputAvalon read data bus

Block diagram

Data Unit
sdai
sdao
Control Logic
Clock Unit
scli
sclo
Avalon Interface
writedata (7:0)
readdata (7:0)
write
read
chipselect
clk
reset
irq

Units

Data Unit

It controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.

Control Logic

Control Logic manages execution of all commands sent via CPU interface. Synchronizes internal data flow.

Clock Unit

It performs I2C SCL clock stretching when DI2CS core is not ready for next transmission. SCLI spikes are filtered by this unit.

Avalon Interface

Avalon Interface performs the interface functions between DI2CS internal blocks and Avalon bus. Allows easy connection of the core to existing Avalon systems.

Performance


Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

ImplementationSpeed
grade
Utilized Area
[LC]
Frequency
[MHz]
APEX20KC-7170150
STRATIX-5170260
CYCLONE-6170220

DI2CS-Avalon implementation results for ALTERA devices. The all features have been included.


Family summary

DesignI2C specificationOperation typeStandard mode   Fast     modeFast Plus modeHigh Speed modeMulti master7 bit address10 bit addressInterrupt gen.Passive elements interfaceMicrocontroller interfaceUser defined timing
100 kb/s400 kb/s1 Mb/s3.4 Mb/s
DI2CMv. 3.0MASTER++++++++-++
DI2CSv. 3.0SLAVE++++++-+-++
DI2CSBv. 3.0SLAVE++++++--+--
DI2CMSv. 3.0MASTER/SLAVE++++++++-++


The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.