I2C Bus Interface - Slave with Avalon interface
The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CS-Avalon core provides an interface between parallel Avalon bus and serial I2C bus. It can works as a slave transmitter or slave receiver depending on working mode determined by a master device. The DI2CS-Avalon core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS-Avalon supports all the transmission speed modes.
The DI2CS-Avalon is a technology independent design that can be implemented in a variety of process technologies.

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- Compliant with Avalon interface specification, Revision 1.0
- Single Avalon input clock for registers and I2C bus serial clock generation
- Conforms to v.3.0 of the I2C specification
- Slave operation
- Slave transmitter
- Slave receiver
- Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Allows operation from a wide range of input clock frequencies
- Simple interface allows easy connection to existing Avalon systems
- Interrupt generation
- User-defined data setup time
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
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- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Cost-effective reliable automotive systems
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 sdai
sdao 
 scli
sclo 
 writedata (7:0)
 write
 read
 chipselect
readdata (7:0) 

| Pin | Type | Description |
| clk | input | Global clock |
| reset | input | Global reset |
| sdai | input | I2C bus data line (input) |
| scli | input | I2C bus clock line (input) |
| writedata (7:0) | input | Avalon write data bus |
| write | input | Avalon write data bus |
| read | input | Avalon read data bus |
| chipselect | input | Avalon chip select |
| irq | output | Interrupt request |
| sdao | output | I2C bus data line (output) |
| sclo | output | I2C bus clock line (output) |
| readdata (7:0) | output | Avalon read data bus |

sdai 
sdao 
scli 
sclo 
 writedata (7:0)
 readdata (7:0)
 write
 read
 chipselect
clk 
reset 
 irq

Data UnitIt controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.
Control LogicControl Logic manages execution of all commands sent via CPU interface. Synchronizes internal data flow.
Clock UnitIt performs I2C SCL clock stretching when DI2CS core is not ready for next transmission. SCLI spikes are filtered by this unit.
Avalon InterfaceAvalon Interface performs the interface functions between DI2CS internal blocks and Avalon bus. Allows easy connection of the core to existing Avalon systems.

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation | Speed grade | Utilized Area [LC] | Frequency [MHz] |
| APEX20KC | -7 | 170 | 150 |
| STRATIX | -5 | 170 | 260 |
| CYCLONE | -6 | 170 | 220 |
DI2CS-Avalon implementation results for ALTERA devices. The all features have been included.

| Design | I2C specification | Operation type | Standard mode | Fast mode | Fast Plus mode | High Speed mode | Multi master | 7 bit address | 10 bit address | Interrupt gen. | Passive elements interface | Microcontroller interface | User defined timing |
| 100 kb/s | 400 kb/s | 1 Mb/s | 3.4 Mb/s |
| DI2CM | v. 3.0 | MASTER | + | + | + | + | + | + | + | + | - | + | + |
| DI2CS | v. 3.0 | SLAVE | + | + | + | + | + | + | - | + | - | + | + |
| DI2CSB | v. 3.0 | SLAVE | + | + | + | + | + | + | - | - | + | - | - |
| DI2CMS | v. 3.0 | MASTER/SLAVE | + | + | + | + | + | + | + | + | - | + | + |
The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping user to select the most suitable IP Core for its application.
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