Altera awards the SOPC Builder Ready certification to IP functions that are ready to integrate with the NIOS embedded processors via the SOPC Builder. These cores support interfaces for the AVALON bus for the Nios processor, and may include software drivers, low-level routines, or other software design files.

The AMPP program presents the "AMPP Approved" stamp, a sign of an intellectual property (IP) core that has successfully passed the high standards of the Altera "AMPP Approved" qualification process.

The "AMPP Approved" stamp is your assurance that an AMPP partner's IP core meets Altera's sales standards and has passed rigorous engineering testing. This testing includes ensuring flawless implementation through Altera's suite of internal and third-party EDA tools, as well as the availability of accurate technical documentation. The "AMPP Approved" stamp assures that partner cores have the following customer deliverables:

• Core source code or encrypted netlist
• Applicable constraint files
• Test benches
• Supporting documentation

AllianceCORE products are passed through a strict Xilinx qualification phase before it is announced. The qualification consists of reviewing a set of deliverables and ensuring a smooth flow through Xilinx tools. All cores are passed through Xilinx tools to arrive at a completely placed and routed design and a downloadable bit stream. For cores with timing requirements, constraints files are provided to the Xilinx tools along with netlists in order to guarantee performance. After place and route, the cores are simulated and verified by the partners to meet all the specifications of a given core. All products are available immediately for purchase in a Xilinx netlist format that is usable in both Xilinx Alliance and ISE/Foundation series development software. Source code version of AllianceCORE products are also available. In addition to checking tool flow, Xilinx works with the partners to ensure clean design practices subject to the cores specifications and requirements. These include usage of specific architectural features to an advantage, avoiding gated clocks, keeping number of clocks to a minimum, keeping designs synchronous, etc.

All Connection Cores are reviewed to determine that they have met Lattice's recommended IP tool flow and high-quality standards. First, the Connection Provider certifies to Lattice that the core has successfully been implemented with Lattice's ispLEVER suite of implementation tools and third-party EDA tools. The Connection provider also certifies that the core has been thoroughly tested to comply with the functional and performance requirements of applicable industry specifications.
Lattice reviews each Connection Core for proper development methodology, and package completeness. We also check that the performance and fit on the Lattice device are appropriate for that particular device and speed grade. Actual performance of any Connection Core is not guaranteed by Lattice, as it is dependent on many factors, including the user's system design.

The OpenMORE assessment program is based on the Reuse Methodology Manual (RMM) second edition, co-authored by Synopsys and Mentor Graphics. OpenMORE for soft IP is based on over 150 rules and guidelines from the RMM which are encapsulated into a weighted spreadsheet for use by design teams to self-assess their IP. Synopsys assigns OpenMORE ratings of one to four stars upon review of the completed OpenMORE assessments. The OpenMORE ratings reflect adoption of the rules and guidelines for the design, verification and delivery of soft IP described in the RMM. Answering the rules and guidelines contained in OpenMORE spreadsheet for an IP core computes a weighted score. Based on the weighted score (%), a rating between 1 and 4 stars is assigned according to the following ranges:

Adjusted Weighted Score %(S)	Number of Stars
S < 60%	No stars
60 <= S < 75
75 <= S < 87
87 <= S < 95
95 <= S

In typical intrusive systems a debugging tool usually consumes for its own needs some system resources e.g.: part of program space, several cells of RAM memory, ports' pins sometimes system is loosing interrupts or the program code is manipulated to support software breakpoints, and so on.
Even simple debugging systems consumes the UART and timer resources to support own tasks. These simple 'emulators' cannot provide trace and other advanced debugging functions, while also being very intrusive in the debugging cycle. Imagine trying to debug an interrupt problem while the 'emulator' is manipulating interrupts itself!

Developing firmware is all about producing code that is 100% reliable in operation and fully understood in how it will perform in adverse conditions. A real non intrusive on-chip debugger that assists user in this task is the most important tool user can have. That is the reason why using of non intrusive systems is so importand, that is also the reason, why the DoCD^TM debugging tool, was designed as a non-intrusive system.

Real-time hardware debugger we call for a tool that is able to detect processor internal properties that are not visible outside the processor without any violation of real-time operations. DoCD^TM gives you the chance to track down hidden bugs within the application running with microcontroller. Internal events such as the reading of the SBUF-control register are not mirrored on the external address-data bus. However, by using special logic to detect operations that affect internal resources, DoCD^TM gives user ability to track such internal events without any violation of real-time operation. There is no need to use a special external logic for the emulation.