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It allows hardware breakpoints, trace, variables watch, multi C sources debugging. The D68XX DoCDTM Debug Software can work as a hardware debugger as well as a software simulator. So some tasks can be validated at software simulation level, and after this step user can continue real-time debugging by uploading code into silicon. The D68XX DoCDTM user can use its favorite C compilers or assemblers for software development, because it supports most of High Level Object files produced by C/ASM compiler tools:
Our intention in developing DoCDTM was assuring customers with possibility of easy system verification and software debugging at no additional charges. Thus we decided to include complete debug system to each D68XX IP Core. Now DCD's customers can get from a one vendor complete solution to make their own D68XX based SoC, with ability to pre-silicon validation and post-silicon software debugging. It's a really unusual situation that designer can get a high quality IP Core and good on-chip debugging tool from the same vendor.
The Debug IP Core is a real-time hardware debugger provides access to whole chip registers, memories and
peripherals connected to DCD's IP Core (D68XX), and controls CPU work by non-intrusive
method.
The Debug IP Core is provided as VHDL or Verilog source code as well as CPLD/FPGA EDIF netlist depending
on the customer requirements. DoCDTM provides a scaled solution, Because many SoC designs have both
power and area limitations. Debug IP Core can be scaled to control gate count. The benefit is fewer
gates for lower power and core size while trading off debug capability. Typically, all of the features
are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation) with a lesser feature set
shipped in final silicon.
The D68XX DoCDTM Software (DS) is a Windows based application. It is fully compatible with all existing
68XX C compilers and Assemblers. The DS allows user to work in two major modes: software simulator mode
and hardware debugger mode. Those two modes assure possibility to pre-silicon software validation in simulation
mode and then real-time debugging of developed software inside silicon - using debugger mode. Once loaded, the
program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions,
or stopped at any of the breakpoints.
Summarized D68XX DoCD Features and options.
A high-performance Hardware Assisted Debugger is connected to the target system containing the
DCD's core either in FPGA or ASIC. HAD2 is a small hardware adapter that manages communication between the Debug
IP Core inside silicon and a host PC running DoCDTM Debug Software.
SOFTWARE BREAKPOINTS: An unlimited number of software breakpoints can be set anywhere in the physical address space of the processor. This means that breakpoints can be set in Program Memory space, RAM and SFRs. If at least one software breakpoint is set program is executed in automatic step by step mode, with checking if certain breakpoint condition is met. Program execution is halted when breakpoint condition is already met, and its execution can be resumed at any time in any appropriate mode. HARDWARE BREAKPOINTS: The number of hardware breakpoints is limited to four in different address spaces. Like software breakpoints, hardware execution breakpoints can be set in Program Memory space, RAM and SFRs. Like their software counter-parts, they stop program execution just prior to an instruction being executed. The difference is found in the method of program execution. In this case program is run with full clock speed (in real-time), and processor is halted when hardware signalizes true breakpoint condition. MIXED MODE BREAKPOINTS: Mixed breakpoint mode is also allowed and it means that software and hardware breakpoints are mixed in the system. This gives user a flexibility in the debugging. For example two different break conditions can be set at the same address space using software and hardware breakpoints. In each breakpoint mode halt means: CPU is halted and instructions are no longer being fetched, all peripherals running and are not affected by halt. SCALED SOLUTION: Because many SoC designs have both power and gate limitations, DCD provides a scaled solution. Debug extensions can be scaled to control gate counts. The benefits are fewer gates, lower power and core size while trading off debug capability. HOST REQUIREMENTS:
A Pentium class computer with minimum 32 MB of memory, 10 MB of free space on Hard Disk, USB port,
and Windows 2000/XP operating systems.  docddataidocddatao
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The following table give a survey about the Debug IP Core area in the FPGA and ASIC devices.
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