• Debug IP Core
• Hardware Assisted Debugger
• Debug Software

The Debug IP Core block provides an in-circuit emulator feature. The Debug IP Core can be provided as VHDL or Verilog source code as well as CPLD/FPGA EDIF netlist depending on the customer requirements. Because many SoC designs have both power and area limitations, DoCD^TM provides a scaled solution. Debug IP Core can be scaled to control gate count. The benefit is fewer gates for lower power and core size while trading off debug capability. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware emulation or FPGA evaluation) with a lesser feature set shipped in final silicon.

The DoCD^TM Software (DS) is a Windows based application. It is fully compatible with nearly all existing PIC C compilers and Assemblers. The DS allows user to work in two major modes: software simulator mode and hardware emulator mode. Those two modes assure possibility to presilicon software validation in simulation mode and then real-time debugging of developed software inside silicon - using emulator mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or ASM-level instructions, or stopped at any of the breakpoints. The DoCD^TM Debug Software supports all DCD's PIC Cores (DRPIC1655X, DFPIC1655X) in the following architectures and particular configurations:

• High Performance RISC - (DF -2 CLK cycle per instruction)
• Pipelined High Performance RISC - (DR -1 CLK cycle per instruction)

A high-performance Hardware Assisted Debugger is connected to the target system containing the DCD's core either in FPGA or ASIC. HAD2 is a small hardware adapter that manages communication between the Debug IP Core inside silicon and a USB port of the host PC running DoCD^TM Debug Software.

An unlimited number of software breakpoints can be set anywhere in the physical address space of the processor. This means that breakpoints can be set in Program Memory space, RAM and SFRs. If at least one software breakpoint is set program is executed in automatic step by step mode, with checking if certain breakpoint condition is met. Program execution is halted when breakpoint condition is already met, and its execution can be resumed at any time in any appropriate mode.

The number of hardware breakpoints is limited to four in different address spaces. Like software breakpoints, hardware execution breakpoints can be set in Program Memory space, RAM and SFRs. Like their software counter-parts, they stop program execution just prior to an instruction being executed. The difference is found in the method of program execution. In this case program is run with full clock speed (in real-time), and processor is halted when hardware signalizes true breakpoint condition.

Mixed breakpoint mode is also allowed and it means that software and hardware breakpoints are mixed in the system. This gives user a flexibility in the debugging. For example two different break conditions can be set at the same address space using software and hardware breakpoints. In each breakpoint mode halt means: CPU is halted and instructions are no longer being fetched, all peripherals running and are not affected by halt.

Because many SoC designs have both power and gate limitations, DCD provides a scaled solution. Debug extensions can be scaled to control gate counts. The benefits are fewer gates, lower power and core size while trading off debug capability.

A Pentium class computer with minimum 32 MB of memory, 10 MB of free space on Hard Disk, USB port, and Windows 2000/XP operating systems.

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The following table give a survey about the Debug IP Core area in the FPGA and ASIC devices.

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