DZ80
8-bit Microprocessor
Documentation
The DZ80 is an advanced, 8-bit microprocessor, with 208 bits of user-accessible registers. It is composed of six general purpose registers, which can be used individually, as either 8-bit or 16-bit register pairs. Additionally, DZ80 supports two sets of accumulator and flag registers. The DZ80 contains also Stack Pointer, program Counter, two index registers, a REFRESH register and an INTERRUPT register. All output signals are fully decoded and timed, to control standard memory or peripheral circuits. The DZ80 is supported by a wide range of peripherals.
DZ80 is fully customizable - it is delivered in the exact configuration, to meet user's requirements. There is no need to pay extra, for unused features and wasted silicon.
It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
CPU Features
- Fully compatible with Z80 industry standard
- Fully synthesizable, static synchronous de-sign with no internal tri-states
- No internal reset generator or gated clock
- Scan test ready
- Technology independent HDL source code
- Core can be fully customized
Symbol
clk porm1
mreq
iorq
rfsh
halt
int nmi wait
datai (7:0) busrqdatao (7:0)
addr (15:0) 
wr
rd
busack
Pins description
| Pin | Type | Description |
|---|---|---|
| clk | input | Global clock |
| por | input | Global reset Power On Reset |
| int | input | Interrupt Request is generated by I/O devices. The CPU honors a request at the end of the current instruction if the internal software-controlled interrupt enable flip-flop is enabled. |
| nmi | input | NMI has a higher priority than INT. NMI is always recognized at the end of the current instructtion, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H. |
| wait | input | WAIT communicates to the CPU that the addressed memory or I/O devices are not ready for a data transfer. The CPU communicates to enter a WAIT state as long as this signal is active. Extended WAIT periods can prevent the CPU from properly refreshing dynamic memory. |
| datai (7:0) | input | |
| busrq | input | Bus Request has a higher priority tthan NMI and is always recognized at the end of the current machine cycle. BUSRQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines. |
| m1 | output | M1 together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. M1 together with IORQ, indicates an interrupt acknowledge cycle. |
| mreq | output | MREQ indicates that the address bus holds a valid address for memory read or memory write operation. |
| iorq | output | IORQ indicates that lower half of address bus holds a valid I/O address for an I/O read or write operation. IORQ is also generated concurrently with M1 during an interrupt acknowledge cycle to indicate an interrupt response vector can be laced on the data bus. |
| rfsh | output | RFSH together with MREQ indicates that the lower seven bits of the system"s address bus can be used as a refresh address to the system"s dynamic memories. |
| halt | output | HALT indicates that the CPU has executed a HALT instruction and is waiting for either a non-maskable or a maskable interrupt before oparation can resume. During HALT, the CPU axecutes NOP"s to maintain memory refresh. |
| datao (7:0) | output | |
| addr (15:0) | output | Address bus provides the address for memory data bus exchanges, and for I/O device exchanges. |
| wr | output | WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or I/O locations. |
| rd | output | RD indicates that the CPU wants to read data from memory or I/O location pointed by the address bus. The memory or I/O should use this signal to gate data onto the CPU data bus. |
| busack | output | Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ, RD and WR have entered their high-impedance states. The external circuitry can now control these lines. |
Block Diagram
| Control UnitPerforms the core synchronization and data flow control. This module manages the execution of all instructions. The Control Unit also manages execution of HALT state and waking up the processor from the HALT mode. |
m1
mreq
iorq
rfsh
halt
| Instruction DecoderPerforms an instruction opcode decoding and the control functions for all other blocks. |
| Interrupt ControllerManages execution of maskable and nonmaskable interrupts. It contains a Interrupt Enable register. Interrupt controller is responsible for the special M1 Cycle generation and wait states implementation, during interrupt service. |
intnmi| Bus ControllerData Memory and SFR's (Special Function Register) interface, controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, Index registers and related logic. |
wait
datai (7:0)datao (7:0)addr (15:0)wrrdbusrqbusack| ALUArithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. Contains accumulator CPU registers and related logic, such as arithmetic and logic unit. ALU communicates with internal registers and the external data bus, by using internal data bus. |
clk
por