Digital Core Design

D68000

16/32-bit Microprocessor

Documentation

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Performance
Info
Pins description
Block diagram
Units

The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, its code is compatible with the MC68008, upward code compatible with MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instructions set, which allows to execute the program with higher performance, than a standard 68000 core.
The D68000 is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.

A special testing platform has been built to run D68000 with uCLinux Operating System. For more details, please check this link.

Watch the D68000 presentation on DCD's You Tube:

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

Implementation	Speed grade	Utilized Area [Slices]	Frequency [MHz]
VIRTEX-E	-8	3317	38
VIRTEX-II	-5	3366	58
VIRTEX-II pro	-7	3415	65

D68000 implementation results for XILINX devices.
All features have been included.

Implementation	Speed grade	Utilized Area [LC]	Frequency [MHz]
APEX20KC	-7	6332	37
STRATIX	-5	6862	49
CYCLONE	-6	6604	44

D68000 implementation results for ALTERA devices.
All features have been included.

CPU Features

Software compatible with 68000 industry standard
MULS, MULU take 28 clock periods
DIVS, DIVU take 28 clock periods
Optimized shifts and rotations
Idle cycles removed to improve performance
Shorter effective address calculation time
Bus cycle timings identical to 68000
32 bit data and address registers
14 addressing modes:
- Direct:
  - Data register direct
  - Address register direct
- Indirect:
  - Register indirect
  - Postincrement register indirect
  - Predecrement register indirect
  - Register indirect with offset
  - Indexed register indirect with offset
- PC relative:
  - Relative with offset
  - Relative with index and offset
- Absolute data:
  - Absolute short
  - Absolute long
- Immediate data:
  - Immediate
  - Quick immediate
  - Implied
5 data types supported:
- bits
- BCD
- bytes, words and long words
Arithmetic Logic Unit includes:
- 8,16,32-bit arithmetic & logical operations
- 16x16 bit signed and unsigned multiplication
- 32/16 bit signed and unsigned division
- Boolean operations
Interrupt controller:
- 7 priority levels interrupt controller
- Unlimited number of virtual interrupt sources
- Vectored and auto-vectored modes
Memory interface includes:
- Up to 4 GB of address space
- 16-bit data bus
- Asynchronous bus control
M6800 family synchronous interface
- 3- and 2- wire bus arbitration
- Supervisor and user modes
Fully synthesizable
Static synchronous design

Symbol

clk

rsti

halti

rsto

halto

ipl (2:0)

datai (15:0)

dtack

bgack

berr

vpa

addr (23:0)

datao (15:0)

addrz

dataz

fc (2:0)

ctrlz

lds

uds

rdwr

vma

epd

Pins description

Pin	Type	Description
clk	input	Global clock
rsti	input	Global reset input
halti	input	Halt input
ipl (2:0)	input	Interrupt control
datai (15:0)	input	Data bus input
dtack	input	Data transfer acknowledge
br	input	Bus request
bgack	input	Bus grant acknowledge
berr	input	Bus error
vpa	input	Valid peripheral address
rsto	output	Reset output
halto	output	Halt output
addr (23:0)	output	Address data bus
datao (15:0)	output	Data bus output
addrz	output	Turns DATA bus into "Z" state
dataz	output	Turns ADDRESS bus into "Z" state
fc (2:0)	output	Processor function code
ctrlz	output	Turns AS, RDWR, UDS, LDS, VMA, FC(2:0) into "Z" state
as	output	Address strobe
lds	output	Lower data byte strobe
uds	output	Upper data byte strobe
rdwr	output	Read write signal
bg	output	Bus grant
vma	output	Valid memory address
epd	output	Enable peripheral device

Block Diagram

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.

Control UnitControl Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. Contains SR (status register is consisted of two portions supervisor byte and user byte) and its related logic.

rsti

rsto

halti

halto

Interrupt ControllerInterrupt Controller - Interrupt Control module is responsible for the interrupt manage system for the external/internal interrupts and exceptions processing. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.

ipl (2:0)

ALUALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator and related logic, such as arithmetic unit, logic unit, multiplier and divider. BCD operation are executed in this unit and condition code flags (N-negative, Z-zero, C-carry V-overflow) for most instructions.

Data registersData registers - Contains 32-bit data registers D0 to D7 and related logic to perform byte, word and long data operations.

Memory InterfaceMI Contains memory access related registers. It performs the memory addressing instructions code fetching and data transfers. It is responsible for all external bus cycle actions, such as: read/write, repeated read/write, halt and resume of bus cycles, bus arbitration provided by 3- and 2- wire system, correct bus and address errors handling, wait states cycle insertion and M6800 synchronous cycle generation.

addr (23:0)

datao (15:0)

datai (15:0)

addrz

dataz

fc (2:0)

ctrlz

lds

uds

rdwr

dtack

bgack

berr

vpa

vma

epd

Address registersAddress registers - Contain 32-bit A0 to A6 address registers, two stack pointers USP (user SP) and SSP (Supervisor SP), 32-bit Program counter and related logic, to perform word and long address operations. An effective address operations are executed in this unit.

ShifterShifter - Performs shifting operations for the appropriate instructions, mainly for rotation, shift and bit operations.

clk

D68k data bus Internal 32-bit data bus used to transfer data

D68k address bus Internal 32-bit address bus used to transfer addresses

Units

Opcode Decoder

Performs an opcode decoding instruction and control functions for all other blocks.

Control Unit

Control Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. Contains SR (status register is consisted of two portions supervisor byte and user byte) and its related logic.

Interrupt Controller

Interrupt Controller - Interrupt Control module is responsible for the interrupt manage system for the external/internal interrupts and exceptions processing. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.

ALU

ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator and related logic, such as arithmetic unit, logic unit, multiplier and divider. BCD operation are executed in this unit and condition code flags (N-negative, Z-zero, C-carry V-overflow) for most instructions.

Data registers

Data registers - Contains 32-bit data registers D0 to D7 and related logic to perform byte, word and long data operations.

Memory Interface

MI Contains memory access related registers. It performs the memory addressing instructions code fetching and data transfers. It is responsible for all external bus cycle actions, such as: read/write, repeated read/write, halt and resume of bus cycles, bus arbitration provided by 3- and 2- wire system, correct bus and address errors handling, wait states cycle insertion and M6800 synchronous cycle generation.

Address registers

Address registers - Contain 32-bit A0 to A6 address registers, two stack pointers USP (user SP) and SSP (Supervisor SP), 32-bit Program counter and related logic, to perform word and long address operations. An effective address operations are executed in this unit.

Shifter

Shifter - Performs shifting operations for the appropriate instructions, mainly for rotation, shift and bit operations.