Digital Core Design

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D68000

16/32-bit Microprocessor

The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, its code is compatible with the MC68008, upward code compatible with MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instructions set, which allows to execute the program with higher performance, than a standard 68000 core.
The D68000 is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.

A special testing platform has been built to run D68000 with uCLinux Operating System. For more details, please check this link.

Watch the D68000 presentation on DCD's You Tube:

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Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

Implementation Speed
grade
Slices/LUTs Frequency
[MHz]
VIRTEX -6 3356/- 32
VIRTEX-E -8 3317/- 38
VIRTEX-II -5 3366/- 58
VIRTEX-IIP -7 3415/- 65
VIRTEX-7 -3 2710/7020 101
SPARTAN-6 -3 2460/6980 85 
KINTEX-7 -3 2510/6999 107

D68000 implementation results for XILINX devices. 
All features have been included. 

Implementation Speed
grade
Utilized Area
[LC]
Frequency
[MHz]
APEX20KC -7 6332 37
STRATIX -5 6862 49
CYCLONE -6 6604 44

D68000 implementation results for ALTERA devices. 
All features have been included. 


CPU Features


Symbol

 clk
 rsti
 halti
rsto 
halto 
 ipl (2:0)
 datai (15:0)
 dtack
 br
 bgack
 berr
 vpa
addr (23:0) 
datao (15:0) 
addrz 
dataz 
fc (2:0) 
ctrlz 
as 
lds 
uds 
rdwr 
bg 
vma 
epd 

Pins description

PinTypeDescription
clkinputGlobal clock
rstiinputGlobal reset input
haltiinputHalt input
ipl (2:0)inputInterrupt control
datai (15:0)inputData bus input
dtackinputData transfer acknowledge
brinputBus request
bgackinputBus grant acknowledge
berrinputBus error
vpainputValid peripheral address
rstooutputReset output
haltooutputHalt output
addr (23:0)outputAddress data bus
datao (15:0)outputData bus output
addrzoutputTurns DATA bus into "Z" state
datazoutputTurns ADDRESS bus into "Z" state
fc (2:0)outputProcessor function code
ctrlzoutputTurns AS, RDWR, UDS, LDS, VMA, FC(2:0) into "Z" state
asoutputAddress strobe
ldsoutputLower data byte strobe
udsoutputUpper data byte strobe
rdwroutputRead write signal
bgoutputBus grant
vmaoutputValid memory address
epdoutputEnable peripheral device

Block Diagram

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
Control UnitControl Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. Contains SR (status register is consisted of two portions supervisor byte and user byte) and its related logic.
rsti
rsto
halti
halto
Interrupt ControllerInterrupt Controller - Interrupt Control module is responsible for the interrupt manage system for the external/internal interrupts and exceptions processing. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.
ipl (2:0)
ALUALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator and related logic, such as arithmetic unit, logic unit, multiplier and divider. BCD operation are executed in this unit and condition code flags (N-negative, Z-zero, C-carry V-overflow) for most instructions.
Data registersData registers - Contains 32-bit data registers D0 to D7 and related logic to perform byte, word and long data operations.
Memory InterfaceMI Contains memory access related registers. It performs the memory addressing instructions code fetching and data transfers. It is responsible for all external bus cycle actions, such as: read/write, repeated read/write, halt and resume of bus cycles, bus arbitration provided by 3- and 2- wire system, correct bus and address errors handling, wait states cycle insertion and M6800 synchronous cycle generation.
addr (23:0)
datao (15:0)
datai (15:0)
addrz
dataz
fc (2:0)
ctrlz
as
lds
uds
rdwr
dtack
br
bg
bgack
berr
vpa
vma
epd
Address registersAddress registers - Contain 32-bit A0 to A6 address registers, two stack pointers USP (user SP) and SSP (Supervisor SP), 32-bit Program counter and related logic, to perform word and long address operations. An effective address operations are executed in this unit.
ShifterShifter - Performs shifting operations for the appropriate instructions, mainly for rotation, shift and bit operations.
clk
D68k data bus Internal 32-bit data bus used to transfer data
D68k address bus Internal 32-bit address bus used to transfer addresses

Units

Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit
Control Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. Contains SR (status register is consisted of two portions supervisor byte and user byte) and its related logic.
Interrupt Controller
Interrupt Controller - Interrupt Control module is responsible for the interrupt manage system for the external/internal interrupts and exceptions processing. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.

ALU
ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator and related logic, such as arithmetic unit, logic unit, multiplier and divider. BCD operation are executed in this unit and condition code flags (N-negative, Z-zero, C-carry V-overflow) for most instructions.
Data registers
Data registers - Contains 32-bit data registers D0 to D7 and related logic to perform byte, word and long data operations.
Memory Interface
MI Contains memory access related registers. It performs the memory addressing instructions code fetching and data transfers. It is responsible for all external bus cycle actions, such as: read/write, repeated read/write, halt and resume of bus cycles, bus arbitration provided by 3- and 2- wire system, correct bus and address errors handling, wait states cycle insertion and M6800 synchronous cycle generation.

Address registers
Address registers - Contain 32-bit A0 to A6 address registers, two stack pointers USP (user SP) and SSP (Supervisor SP), 32-bit Program counter and related logic, to perform word and long address operations. An effective address operations are executed in this unit.
Shifter
Shifter - Performs shifting operations for the appropriate instructions, mainly for rotation, shift and bit operations.