The DF6803 - synthesisable SOFT Microcontroller IP Core is fully software compatible to the Motorola MC6803. The DF6803 has an enhanced internal architecture, which allows it to execute the code approximately 4 times faster, than original 6803 running at the same clock frequency.
The DF6803 has a built-in real time hardware on-chip debugger, the DoCDTM, which allows easy software debugging and validation.
The DF6803 is fully customizable - it is delivered in the exact configuration, to meet users requirements. There is no need to pay extra, for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
The DoCDTM provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger
Family summary
| Family | IP Core |
Architecture type |
Memory space | DoCDTM | UART (SCI) | SPI M/S | IO Ports |
Watchdog Timer |
Timer | Compare / Capture |
Pulse accumulator |
READY pin |
Chip Selects | Gatecount |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| HC05, HC08 | DF6805 | fast | 64k | + | + | - | 4 | + | 1 | 2/2 | - | + | - | 7000 |
| - | DF6808 | fast | 64k | + | + | - | 4 | + | 1 | 2/2 | - | + | - | 8300 |
| - | D68HC05 | legacy | 64k | + | + | + | 4 | + | 1 | 1/1 | - | - | - | - |
| - | D68HC08 | legacy | 64K | + | + | + | 4 | + | 1 | 2/1 | - | - | - | 10000 |
| HC11 | DF6811E | fast | 64k | + | + | + | 5 | + | 1 | 5/4 | + | + | - | 12000 |
| - | DF6811F | fast | 64k | + | + | + | 7 | + | 1 | 5/4 | + | + | - | 14000 |
| - | DF6811K | fast | 1M | + | + | + | 10 | + | 3 | 13/6 | + | + | - | 21000 |
| - | D68HC11E | legacy | 64k | + | + | + | 5 | + | 1 | 5/4 | + | - | - | 13000 |
| - | D68HC11K | legacy | 1M | + | + | 1 | 10 | + | 3 | 13/6 | + | - | 4 | 21000 |
| - | D68HC11F | legacy | 64k | + | + | + | 7 | + | 1 | 5/4 | - | - | 4 | 13500 |
| 6802, 6803 | DF6802 | fast | 64k | + | - | - | - | - | - | - | - | - | - | - |
| - | DF6803 | fast | 64k | + | + | + | 4 | - | 1 | + | - | - | - | - |
| - | D6802 | legacy | 64k | + | - | - | - | - | - | - | - | - | - | 3600 |
| - | D6803 | legacy | 64k | + | + | + | 4 | - | 1 | + | - | - | - | 6000 |
The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.
CPU Features
- Improved, 4 times faster architecture
- Software compatible with industry standard MC6803
- I/O Wrapper making it pin compatiblecore
- Power saving mode: WAI
- Fully synthesizable
- Static synchronous design
- No internal tri-states
- Scan test ready
Symbol
port1 port2 port3 port4
halt irq nmi docddatai clkdocddocddatao
docdclk
iramdatai (7:0) xdatai (7:0)iramoe
iramwe
xwe
xoe
addr (15:0)
datao (7:0)
Pins description
| Pin | Type | Description |
|---|---|---|
| port1 | input | Bidirectional Port 1 |
| port2 | input | Bidirectional Port 2, shared with SCI and programmable timer devices |
| port3 | input | Bidirectional Port 3, shared with Low address Byte and Data bus. (Demultiplexed Address/Data bus is also possible) |
| port4 | input | Bidirectional Port 4, shared with high address byte in Expanded mode |
| halt | input | Halt clock system |
| irq | input | Interrupt input |
| nmi | input | Non-maskable interrupt input |
| docddatai | input | DoCDTM serial data input |
| clkdocd | input | Clock signal to DoCDTM On chip Debugger module. This separate clock line allow DoCDTM to operate during the SLEEP mode (major clock CLK is stopped). |
| iramdatai (7:0) | input | Internal Data memory bus input |
| xdatai (7:0) | input | External memory bus input |
| docddatao | output | DoCDTM serial data output |
| docdclk | output | DoCDTM serial data clock line |
| iramoe | output | Internal Program / Data memory output enable |
| iramwe | output | Internal Program / Data memory write enable |
| xwe | output | External memory write enable |
| xoe | output | External memory output enable |
| addr (15:0) | output | Common address bus |
| datao (7:0) | output | Data bus output |
Block Diagram
| SCIThe SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit and stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag. |
| I/O PortsGeneral Purpose I/O Ports. When enabled, the I/O Ports are shared with particular on chip peripherals: SCI and TIMER. |
port1
port2
port3
port4
| Timer with Compare CaptureThe programmable timer is based on free-running 16-bit counter and input capture/output compare circuitry. The timer can be used for many purposes, including measuring pulse length of two input signals and generating two output signals. The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contain the high and the low byte of that functional block. Accessing the low byte of a specific timer function, allows full control of that function, however, an access of the high byte, inhibits that specific timer function, until the byte is also accessed. |
| Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks. |
| Control UnitPerforms the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages HALT input pin events. |
halt
| Interrupt ControllerInterrupt Controller Interrupt Control module is responsible for the interrupt manage system, for the processing of the external and internal interrupts and exceptions. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation. |
irqnmi
| DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off. The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped). |
docddataidocddataodocdclkclkdocd
| Bus ControllerProgram Memory, Data Memory interface, controls access into the program and data memories. It contains Program Counter (PC), Stack Pointer (SP) register, and related logic. |
iramoe
iramwe
iramdatai (7:0)
xdatai (7:0)
xwe
xoe
addr (15:0)
datao (7:0)
| ALUArithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), Index register X and related logic, like arithmetic unit, logic unit, multiplier and divider. |
| SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture. |
| Data bus Internal 8-bit data bus. |
Units
SCI
The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit and stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag.I/O Ports
General Purpose I/O Ports. When enabled, the I/O Ports are shared with particular on chip peripherals: SCI and TIMER.Timer with Compare Capture
The programmable timer is based on free-running 16-bit counter and input capture/output compare circuitry. The timer can be used for many purposes, including measuring pulse length of two input signals and generating two output signals. The timer has a 16-bit architecture, hence each specific functional segment is represented by two 8-bit registers. These registers contain the high and the low byte of that functional block. Accessing the low byte of a specific timer function, allows full control of that function, however, an access of the high byte, inhibits that specific timer function, until the byte is also accessed.Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.Control Unit
Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages HALT input pin events.Interrupt Controller
Interrupt Controller Interrupt Control module is responsible for the interrupt manage system, for the processing of the external and internal interrupts and exceptions. It manages auto-vectored interrupt cycles, priority resolving and correct vector numbers creation.DoCDTM
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).