Documentation
The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of short distance data transmission between many devices. The DI2CS core provides an interface between a microprocessor/microcontroller and an I2C bus. It can work as a slave transmitter or slave receiver, depending on working mode determined by a master device. The DI2CS core incorporates all features required by the latest I2C specification including clock synchronization, arbitration and High-speed transmission mode. The DI2CS supports all the transmission speed modes.
The DI2CS is a technology independent design which can be implemented in a variety of process technologies.
Family summary
| Design | I2C specification | Operation type | Standard mode | Fast mode | Fast Plus mode | High Speed mode | Multi master | 7 bit address | 10 bit address | Interrupt gen. | Passive elements interface | Microcontroller interface | User defined timing |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 100 kb/s | 400 kb/s | 1 Mb/s | 3.4 Mb/s | ||||||||||
| DI2CM | v3.0 | MASTER | + | + | + | + | + | + | + | + | - | + | + |
| DI2CMS | v3.0 | MASTER/SLAVE | + | + | + | + | + | + | + | + | - | + | + |
| DI2CS | v3.0 | SLAVE | + | + | + | + | + | + | - | + | - | + | + |
| DI2CSB | v3.0 | SLAVE | + | + | + | + | + | + | - | - | + | - | - |
The main features of each I2C bus controllers family members have been summarized in table above. It gives a briefly member characterization helping you to find the most suitable IP Core for the application.
Performance
Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.
| Implementation |
Speed grade |
Utilized Area [Slices] |
Frequency [MHz] |
|---|---|---|---|
| SPARTAN-IIE | -7 | 78 | 133 |
| SPARTAN-3 | -5 | 78 | 133 |
| SPARTAN-3E | -4 | 78 | 127 |
| VIRTEX-E | -8 | 80 | 138 |
| VIRTEX-II | -6 | 80 | 140 |
| VIRTEX-II pro | -7 | 81 | 264 |
| VIRTEX-4 | -12 | 81 | 322 |
DI2CS implementation results for XILINX devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [LUT/PFU] |
Frequency [MHz] |
|---|---|---|---|
| EC | -5 | 191/51 | 166 |
| ECP | -5 | 191/51 | 167 |
| XP | -5 | 191/51 | 148 |
| ECP2 | -7 | 183/50 | 245 |
| ECP2M | -7 | 153/49 | 258 |
| SC | -7 | 167/50 | 284 |
| XP2 | -7 | 153/49 | 220 |
DI2CS implementation results for LATTICE devices.
All features have been included.
| Implementation |
Speed grade |
Utilized Area [LC] |
Frequency [MHz] |
|---|---|---|---|
| APEX20KC | -7 | 170 | 150 |
| STRATIX | -5 | 170 | 260 |
| CYCLONE | -6 | 170 | 220 |
DI2CS implementation results for ALTERA devices.
All features have been included.
Key Features
- Conforms to v.3.0 of the I2C specification
- Slave operation
- Slave transmitter
- Slave receiver
- Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- Fast Plus (up to 1 Mb/s)
- High Speed (up to 3,4 Mb/s)
- Allows operation from a wide range of input clock frequencies
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Interrupt generation
- User-defined data setup time
- Available system interface wrappers:
- AMBA - APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
Applications
- Embedded microprocessor boards
- Consumer and professional audio/video
- Home and automotive radio
- Low-power applications
- Communication systems
- Cost-effective reliable automotive systems
Symbol
scli sdai
datai (7:0) rd we address (1:0) csPins description
| Pin | Type | Description |
|---|---|---|
| scli | input | I2C bus clock line (input) |
| sdai | input | I2C bus data line (input) |
| datai (7:0) | input | Processor data bus (input) |
| rd | input | Processor read strobe |
| we | input | Processor write strobe |
| address (1:0) | input | Processor address lines |
| cs | input | Chip select |
| sclo | output | I2C bus clock line (output) |
| sdao | output | I2C bus data line (output) |
| datao (7:0) | output | Processor data bus (output) |
| irq | output | Processor interrupt line |
Block Diagram
| Clock UnitIt performs I2C SCL clock stretching when DI2CS core is not ready for next transmission. SCLI spikes are filtered by this unit. |
| Control LogicControl Logic manages execution of all commands sent via CPU interface. Synchronizes internal data flow. |
| Data UnitIt controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit. |
| CPU InterfaceCPU Interface performs the interface functions between DI2CS internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system. |
datai (7:0)datao (7:0)rdweaddress (1:0)csirq
| DI2CS data DI2CS data bus |