Digital Core Design

The Power of Intellectual Property

D16950

Expanded UART with FIFO, hard and soft flow control, synchronous mode

    Documentation
    Go to

    The D16950 is a soft Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the OX16C950. It allows serial transmission in two modes: UART mode and FIFO mode. In the second one internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. Our efficient Core performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The processor can read the complete status of the UART at any time, during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). D16950 includes a programmable baud rate generator, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic. We also equipeed our Core with complete MODEM-control capability and processor-interrupt system. Interrupts can be programmed in accordance to your requirements, minimizing the computing required to handle the communications link. D16950 core includes all 16450, 16550, 16650 and 16750 features and additional functions. D16950 has ICR registers that gives additional capabilities of UART work configuration. Data transmission may be synchronized by external clock connected to RI (for receiver and transmitter) or to DSR (only for receiver) pin. NMR register allows to enable 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers. Trigger level registers may be set any value from 1 to 127.
    As all our UART Cores, D16950 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
    This efficient solution is a technology independent design that can be implemented in a variety of process technologies.

    In the FIFO mode, there is a selectable autoflow control feature, that can significantly reduce software overload and increase system efficiency automatically, by controlling serial data flow through the RTS output and the CTS input signals.

    The Core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless it's also proprietary solution for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface, D16950 core implementation and verification are very simple, just by elimination a number of clock trees in complete system.


    Family summary

    UART Feature D16450 D16550 D16750 D16552 D16752 D16950
    FIFO Size - 2*16 2*64 4*16 x*2*64 2*128
    Multichannel option - - - + + -
    Separate BAUD Clock line + + + + + +
    Modem Control + + + + + +
    False Start Bit detection + + + + + +
    Status report + + + + + +
    Internal diagnostic capabilities + + + + + +
    Prioritized interrupt system + + + + + +
    Break generation and detection + + + + + +
    Fast mode CLK/4 - - o - o +
    Half-Duplex RS485 - - o - o +
    RS485 buffer enable - + + - + +
    IRDA support - - o + - +
    Additional CLK prescaler - - - - + -
    1284 Parallel Port - - - + - -
    Hardware flow control RTS/CTS - - + - + +
    Software flow control Xon/Xoff - - - - + +
    Isochronous mode - - - - - +
    Detector o bad data in receiver FIFO - + + + + +
    Special character detection - - - - + +
    Software channel reset - - - - - +
    4 byte device ID - - - - - +
    Trigger levels for receiver and transmitter - - - - - +
    Hardware flow control DTS/DTR - - - - - +
    Optional FIFO size extension to 512 bytes - - + - + -

    The main features of each UART family member have been summarized in table above. It gives a briefly member characterization helping you to select the most suitable IP Core for your application.

    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade    		 Area
    [TILES]    		 Frequency
    [MHz]
    FUSION - 2520 64
    ProASIC3 - 2520 64
    ProASIC3E - 2520 70
    IGLOO - 2576 47
    IGLOO+ - 2576 45
    IGLOOe - 2576 40

    D16950 implementation results for ACTEL devices.  

    Implementation Speed
    grade    		 Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-IIE - 657 57
    SPARTAN-III - 655 83
    SPARTAN-IIIE - 655 90
    SPARTAN-VI - 278 90
    VIRTEX-II - 637 100
    VIRTEX-IV - 635 143
    VIRTEX-V - 300 202
    VIRTEX-VI - 300 183

    Implementation results of the D16950 in XILINX devices.
    All features have been included.

    Implementation Speed
    grade    		 Area
    [LC]    		 Frequency
    [MHz]
    CYCLONE - 1041+2RAM 123
    CYCLONE II - 984+2RAM 127
    CYCLONE III - 982+2RAM 115
    CYCLONE IV - 1071+2RAM 154
    STRATIX - 1041+2RAM 127
    STRATIX II - 679+2RAM 185
    STRATIX II GX - 681+2RAM 190
    STRATIXIV - 732+2RAM 330

    D16950 implementation results for ALTERA devices.
    All features have been included. 


    Key Features
    • Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
    • Configuration capability
    • Separate configurable BAUD clock line
    • Majority Voting Logic
    • Two modes of operation: UART mode and FIFO mode
      • In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
      • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
    • Configurable FIFO size up to 512 levels
    • Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
    • Independently controlled transmit, receive, line status and data set interrupts
    • False start bit detection
    • 16 bit programmable baud generator
    • Independent receiver clock input
    • MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
    • Programmable Hardware Flow Control through RTS and CTS
    • Programmable Flow Control using DTR and DSR
    • Programmable in-band Flow Control using XON/XOFF
    • Programmable special characters detection
    • Trigger levels for TX and RX FIFO
    • Interrupts and automatic in-band and out-off-band flow control
    • Fully programmable serial-interface characteristics:
      • 5-, 6-, 7-, 8- or 9-bit characters
      • Even, odd, or no-parity bit generation and detection
      • 1-, 1.5-, or 2-stop bit generation
      • Internal baud generator
      • Detection of bad data in receiver FIFO
    • Clock prescaler from 1 to 31,875
    • Enhanced isochronous clock option
    • 9- bit data mode
    • Software reset
    • Complete status reporting capabilities
    • Line break generation and detection. Internal diagnostic capabilities:
      • Loop-back controls for communications link fault isolation
      • Break, parity, overrun, framing error simulation
    • Full prioritized interrupt system controls
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • Serial Data communications applications
    • Modem interface
    • Embedded microprocessor boards

    Configuration

    The following parameters of the D16950 core can be easily adjusted to requirements of proprietary application and technology. Core configuration can be effortlessly done by changing appropriate constants in package file. There is no need to change any part of the code.

    • FIFO Size: normal 16/128 / large, up to 512

    Symbol

     clk
     rst
     rclk
     fifosel
     si
    so 
    temt 
     addr (2:0)
     datai (7:0)
     rd
     wr
     cs
    datao (7:0) 
    ready 
    ddis 
    txrdy 
    rxrdy 
     cts
     dsr
     dcd
     ri
    rts 
    dtr 
    out1 
    out2 
     clksel
    boudout 
     intsel
    int 

    Pins description
    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    rclkinputReceiver clock
    fifoselinputFIFO select
    siinputSerial data input
    addr (2:0)inputAddress Bus
    datai (7:0)inputData input
    rdinputRead
    wrinputWrite
    csinputCable Select
    ctsinputClear to send input
    dsrinputData set ready input
    dcdinputData carrier detect input
    riinputRing indicator input
    clkselinputClock select
    intselinputInterrupt select input
    sooutputSerial data output
    temtoutputTransmitter Empty - used to control RS485 buffer
    datao (7:0)outputData output
    readyoutputReady
    ddisoutputDriver disable output
    txrdyoutputTX ready
    rxrdyoutputRX ready
    rtsoutputRequest to send output
    dtroutputData terminal ready output
    out1outputOutput 1
    out2outputOutput 2
    boudoutoutputBoud rate output
    intoutputInterrupt output

    Block Diagram
    Receiver ControlReceiving starts, when the falling edge on Serial Input (SI) during IDLE State is detected. After starting, the SI input is sampled every 16 internal baud cycles, as it is shown in figure below. When the logic 1 state is detected during START bit it means that the False Start bit was detected and receiver back to the IDLE state.
    rclk
    fifosel
    si
    Receiver FIFOThe Rx FIFO is 16 levels (16550), 64 levels (16750) or 128 levels (16950) deep. It receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. These data entering the Rx shift register will set the Overrun Error flag.
    Transmitter FIFOThe Tx portion of the UART transmits data through SO, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it is currently full. Loading to the Tx FIFO will be enabled again, as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.
    Transmitter ControlTransmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    so
    temt
    Data Bus BufferData Bus Buffer accepts inputs from the system bus and generates control signals for the other D16950 functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WE signals are active low and are qualified by CS; RD and WE are ignored unless the D16950 has been selected by holding CS low.
    addr (2:0)
    datai (7:0)
    datao (7:0)
    rd
    wr
    cs
    ready
    ddis
    txrdy
    rxrdy
    Modem Control LogicModem Control Logic monitors the interface with the MODEM, data set or a peripheral device emulating MODEM.
    rts
    cts
    dtr
    dsr
    dcd
    ri
    out1
    out2
    Baud GeneratorThe D16950 contains a programmable 16 bit baud generator, that divides clock input by a divisor in the range between 1 and (216–1). Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the Core in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM to prevent long counts on initial load. In addition, prescaler register is provided. It can further divide the clock by values in the range 1,0 to 31,875 in steps of 0,125. Other additional is Time Clock Register (TCR), which allows to set the sampling clock between 4 and 16 values. This options of baud rate capable any input clock frequency up to 60MHz.
    clksel
    boudout
    Interrupt ControllerD16950 consists of fully prioritized interrupt system controller. It is enabled by INTSEL pin. It monitors interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Status (ISR) registers.
    intsel
    int
    clk
    rst
    D16550 D16XXX UART internal data bus

    Units
    Receiver Control
    Receiving starts, when the falling edge on Serial Input (SI) during IDLE State is detected. After starting, the SI input is sampled every 16 internal baud cycles, as it is shown in figure below. When the logic 1 state is detected during START bit it means that the False Start bit was detected and receiver back to the IDLE state.
    Receiver FIFO
    The Rx FIFO is 16 levels (16550), 64 levels (16750) or 128 levels (16950) deep. It receives data until the number of bytes in the FIFO equals the selected interrupt trigger level. At that time, if Rx interrupts are enabled, the UART will issue an interrupt to the CPU. The Rx FIFO will continue to store bytes until it will be completely full. It will not accept any more data when it is full. These data entering the Rx shift register will set the Overrun Error flag.
    Transmitter FIFO
    The Tx portion of the UART transmits data through SO, as soon as the CPU loads a byte into the Tx FIFO. The UART will prevent loads to the Tx FIFO, if it is currently full. Loading to the Tx FIFO will be enabled again, as soon as the next character is transferred to the Tx shift register. These capabilities account for the largely autonomous operation of the Tx. The UART starts the above operations typically with a Tx interrupt.

    Transmitter Control
    Transmitter Control module controls transmission of written to THR (Transmitter Holding Register) character via serial output SO. New transmission starts on the next overflow signal of internal baud generator (the worst case delay: 1 baudout cycle), after writing to THR register or Transmitter FIFO. Transmission control contains THR register and transmitter shift register.
    Data Bus Buffer
    Data Bus Buffer accepts inputs from the system bus and generates control signals for the other D16950 functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WE signals are active low and are qualified by CS; RD and WE are ignored unless the D16950 has been selected by holding CS low.
    Modem Control Logic
    Modem Control Logic monitors the interface with the MODEM, data set or a peripheral device emulating MODEM.

    Baud Generator
    The D16950 contains a programmable 16 bit baud generator, that divides clock input by a divisor in the range between 1 and (216–1). Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the Core in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM to prevent long counts on initial load. In addition, prescaler register is provided. It can further divide the clock by values in the range 1,0 to 31,875 in steps of 0,125. Other additional is Time Clock Register (TCR), which allows to set the sampling clock between 4 and 16 values. This options of baud rate capable any input clock frequency up to 60MHz.
    Interrupt Controller
    D16950 consists of fully prioritized interrupt system controller. It is enabled by INTSEL pin. It monitors interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Status (ISR) registers.