Digital Core Design

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DLIN

LIN Bus Controller

    The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required.
    The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD's controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies.

     

    Watch the DLIN presentation on DCD's You Tube:

    Subskrybuj mój kanał w YouTube


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade
    Utilized Area
    [Tiles]
    Frequency
    [MHz]
    Axcelerator -2 1135 107
    ProAsic3 -2 1652 102
    ProAsic3E -2 1660 99
    Fusion -2 1660 99

    DLIN implementation results for ACTEL devices.
    All features have been included. 

    Implementation Speed
    grade
    Utilized Area
    [LUT/PFU]
    Frequency
    [MHz]
    SC -7 653/317 270
    ECP2 -7 555/314 170
    ECP2M -7 555/314 152
    XP2 -7 555/314 128
    XP -5 425/316 85
    ECP -5 578/316 95
    EC -5 578/316 90

    DLIN implementation results for LATTICE devices.
    All features have been included. 


    Implementation Speed
    grade
    LUTs/
    Slices
    Frequency
    [MHz]
    SPARTAN 3 -5 604/415 121
    SPARTAN 3E -5 574/412 124
    SPARTAN 6 -3 511/167 127
    VIRTEX 4 -12 606/416 202
    VIRTEX 5 -2 455/190 299
    VIRTEX 6 -2 496/178 282
    VIRTEX 7 -2 521/159 416
    VIRTEX ULTRA SCALE -3 539 330
    ARTIX 7 -3 495/184 308
    KINTEX ULTRA SCALE -3 516 330
    KINTEX 7 -1 624 294
    ZYNQ-7000 -3 620 263
    ZYNQ -3 521/228 270

    DLIN implementation results for XILINX devices.
    All features have been included. 

    Implementation Speed
    grade
    Utilized Area
    [LC]
    Frequency
    [MHz]
    Arria GX -6 501/338 166
    Arria IIGX -3 505/337 319
    Arria V -6 326 224
    Cyclone -6 715 159
    Cyclone II -6 715 207
    Cyclone III -6 715 205
    Cyclone IV -6 723 185
    Cyclone V -8 327 172
    Stratix -5 674 147
    Stratix GX -5 462 184
    Stratix II -3 467 266
    Stratix III -2 502 392
    Stratix IV -2 506 409
    Stratix V -3 331 421

    DLIN implementation results for ALTERA devices.
    All features have been included. 


    Info

    LIN (Local Interconnect Network) is a serial communication protocol, which was created to provide a cost efficient bus communication. The LIN standard is developed by LIN consortium (More). It includes the specification of the transmission medium, the interface between development tools, the transmission protocol and the interfaces for software programming. LIN has been created to decrease costs of automotive networks and replace more expensive CAN in simple application (sensors or actuators). The LIN device can be implemented as a master or as a slave node.

    Transmission is initiated by Master Node, which sends the data frame to Slaves Nodes (maximum 15) throat one wire bus.

    Key Features

    • Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification.
    • Automatic LIN Header handling
    • Automatic Re-synchronization
    • Data rate between 1Kbit/s and 20 Kbit/s
    • Master and Slave work mode
    • Time-out detection
    • Extended error detection
    • “Break-in-data” support
    • Available system interface wrappers:
      • AMBA - APB Bus
      • Altera Avalon Bus
      • Xilinx OPB Bus

    Applications

    • Automotive, industrial
    • Embedded communication systems

    Symbol

     clk
     rst
     addr (2:0)
     datai (7:0)
     rd
     wr
     cs
    datao (7:0) 
     rxd
    txd 
    irq 

    Pins description

    PinTypeDescription
    clkinputGlobal clock
    rstinputGlobal reset
    addr (2:0)inputAddress bus
    datai (7:0)inputInput data bus
    rdinputRead data strobe
    wrinputWrite data strobe
    csinputChip select
    rxdinputLIN receive data
    datao (7:0)outputOutput data bus
    txdoutputLIN transmit data
    irqoutputInterrupt signal

    Block Diagram

    Control State UnitControl State unit is responsible for receiving frame from LIN bus. It provides necessary function for data reception, frame timming and error checking.
    Host Controller InterfaceAccepts inputs from the system bus and generates control signals for other DLIN functional blocks. Address bus ADDR(2:0) selects one of register to be read from/written into. Active level of RD, WR and CS can be configurable. RD and WR are ignored unless the DLIN has been selected by activing CS input.
    addr (2:0)
    datai (7:0)
    datao (7:0)
    rd
    wr
    cs
    Baud Rate GeneratorThe DLIN contains a programmable 15 bit baud generator which divides clock input by a divisor in the range beteen 1 and (215-1). The output frequency of the baud generator is 32 x the baud rate. Two registers, called divisor latches DLL and DLH, store the divisor in the 15-bit binary format.
    Receive Controller and Shift RegisterReceive Controller is responsible for receiving frame from LIN bus. Provides necessery function for data reception, frame timming and error checking.
    rxd
    Data BufferStores the received or transmitted data.
    Transmitter Controller and Shift RegisterPerforms transmit management function; data have been sent by LIN bus.
    txd
    Interrupt ControllerInterrupt controller works together with transmitter, receiver and control unit, to indicate DLIN transmission events or errors. User can configure, which events may generate interrupt, by enabled or disabled corresponding bits in Interrupt Enable register. In case of generated interruption, host can find information about the reason, by reading LIN Status Register.
    irq
    clk
    rst
    Control Bus Control bus is intended for control signals connected to each module. Main control is performed by Control State Unit

    Units

    Control State Unit
    Control State unit is responsible for receiving frame from LIN bus. It provides necessary function for data reception, frame timming and error checking.
    Host Controller Interface
    Accepts inputs from the system bus and generates control signals for other DLIN functional blocks. Address bus ADDR(2:0) selects one of register to be read from/written into. Active level of RD, WR and CS can be configurable. RD and WR are ignored unless the DLIN has been selected by activing CS input.
    Baud Rate Generator
    The DLIN contains a programmable 15 bit baud generator which divides clock input by a divisor in the range beteen 1 and (215-1). The output frequency of the baud generator is 32 x the baud rate. Two registers, called divisor latches DLL and DLH, store the divisor in the 15-bit binary format.

    Receive Controller and Shift Register
    Receive Controller is responsible for receiving frame from LIN bus. Provides necessery function for data reception, frame timming and error checking.
    Data Buffer
    Stores the received or transmitted data.
    Transmitter Controller and Shift Register
    Performs transmit management function; data have been sent by LIN bus.

    Interrupt Controller
    Interrupt controller works together with transmitter, receiver and control unit, to indicate DLIN transmission events or errors. User can configure, which events may generate interrupt, by enabled or disabled corresponding bits in Interrupt Enable register. In case of generated interruption, host can find information about the reason, by reading LIN Status Register.