Digital Core Design

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DLCD

LCD/TFT Display Controller

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    The DLCD is a display controller with 24-bit RGB output and synchronization. It may be used for displaying data both on LCD and CRT displays. Pixel data has 8-bit resolution and 24-bit RGB output is generated using external LUT with defined color palette. Our "multimedial" Core is controlled by CPU, which enables usage of external data memory to display data. All parameters are configurable through CPU register interface. The Core was designed to be used with DCD's DP80xxx series of MCU.
    The display controller is perfect for MCU based applications, where static graphic data is displayed, using LCD/TFT matrix or CRT monitor.
    Our unique Core is a technology independent design, that can be implemented in a variety of process technologies.


    Performance

    Each core has been tested in variety of FPGA and ASIC technologies. Its implementation results are summarized below.

    Implementation Speed
    grade    		 Utilized Area
    [Slices]    		 Frequency
    [MHz]
    SPARTAN-III -5 488 128
    SPARTAN-IIIE -5 480 143
    SPARTAN-IIIA -5 490 167
    VIRTEX-E -8 510 112
    VIRTEX-II -6 485 200
    VIRTEX-IV -12 503 258
    VIRTEX-V -3 286 337

    DLCD implementation results for XILINX devices.
    All features have been included. 

    Implementation Speed
    grade    		 Utilized Area
    [LC]    		 Frequency
    [MHz]
    CYCLONE -6 757 148
    CYCLONE-II -6 751 176
    CYCLONE-III -6 740 197
    STRATIX -5 757 156
    STRATIX-II -3 549 214
    STRATIX-III -3 548 332

    DLCD implementation results for ALTERA devices.
    All features have been included. 


    Key Features
    • Maximum resolution 1024 x 1024 pixels
    • 24-bit RGB output, 8-bit pixel with external LUT for color palette
    • Configurable screen parameters
    • Configurable memory data bus width
    • Wait states for memory access
    • Pixel clock divider
    • Display data copying without CPU access
    • Display data accessible for CPU as external data memory
    • Fully synthesizable
    • Static synchronous design and no internal tri-states

    Applications

    • Microcontroller based application
    • Displaying data on LCD/TFT matrix
    • Displaying data on LCD/TFT or CRT monitor

    Symbol

    pclken 
    pclkdivo 
     xdatai (7:0)
     xrd
     xwr
     xcs
     mdatai (31:0)
     xaddr (19:0)
     cdatai (23:0)
    xdatao (7:0) 
    mdatao (31:0) 
    mrd 
    mwr 
    mcs 
    maddr (18:0) 
    byteen (3:0) 
    ready 
    caddr (7:0) 
    r (7:0) 
    g (7:0) 
    b (7:0) 
    hsync 
    vsync 
    de 
     datai (7:0)
     addr (3:0)
     rd
     wr
     cs
    irq 
    datao (7:0) 

    Pins description
    PinTypeDescription
    xdatai (7:0)inputCPU interface, external data memory input bus
    xrdinputCPU interface, external data memory read control
    xwrinputCPU interface, external data memory write control
    xcsinputCPU interface, external data memory chip select
    mdatai (31:0)inputMemory data input bus
    xaddr (19:0)inputCPU interface, external data memory address input
    cdatai (23:0)inputColor palette LUT data bus
    datai (7:0)inputRegister data input
    addr (3:0)inputRegister address bus
    rdinputRegister read control
    wrinputRegister write control
    csinputRegister access chip select
    pclkenoutputDivided pixel clock output enable
    pclkdivooutputDivided pixel clock output
    xdatao (7:0)outputCPU interface, external data memory output bus
    mdatao (31:0)outputMemory data output bus
    mrdoutputMemory read control
    mwroutputMemory write control
    mcsoutputMemory chip select
    maddr (18:0)outputMemory address bus
    byteen (3:0)outputByte enable for memory data bus
    readyoutputReady control
    caddr (7:0)outputColor palette LUT address bus
    r (7:0)outputRed color data output
    g (7:0)outputGreen color data output
    b (7:0)outputBlue color data output
    hsyncoutputHorizontal sync
    vsyncoutputVertical sync
    deoutputData enable for display
    irqoutputInterrupt request
    datao (7:0)outputRegister data output

    Block Diagram
    Clock dividerGenerates divided clock signal for pclkdivo output.
    pclken
    pclkdivo
    Memory controlManages memory access, LUT color palette access, reads pixel data for displaying, controls transactions on external data interface.
    xdatai (7:0)
    xdatao (7:0)
    xrd
    xwr
    xcs
    mdatai (31:0)
    mdatao (31:0)
    mrd
    mwr
    mcs
    xaddr (19:0)
    maddr (18:0)
    byteen (3:0)
    ready
    cdatai (23:0)
    caddr (7:0)
    r (7:0)
    g (7:0)
    b (7:0)
    Sync controlGenerates synchronization signals for display and synchronizes data for display.
    hsync
    vsync
    de
    CPU controlPerforms operation of reading and writing internal registers.
    irq
    datai (7:0)
    datao (7:0)
    addr (3:0)
    rd
    wr
    cs
    DLCD bus Internal conections bus

    Units
    Clock divider
    Generates divided clock signal for pclkdivo output.
    Memory control
    Manages memory access, LUT color palette access, reads pixel data for displaying, controls transactions on external data interface.
    Sync control
    Generates synchronization signals for display and synchronizes data for display.

    CPU control
    Performs operation of reading and writing internal registers.