Digital Core Design

DQ80251

Revolutionary Quad-Pipelined Ultra High Performance Microcontroller

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Family Summary
Performance
Info
Pins description
Block diagram
Units

DQ80251 is a revolutionary Quad-Pipelined ultra high performance, speed optimized soft core, of a 16-bit/32-bit embedded microcontroller. The core has been designed with a special concern for performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit. This product is built based on 11 years of DCD’s know-how, with triumphant 8051 architectures. DQ80251 soft core is 100% binary-compatible with the industry standard 16-bit 80C251 and 8-bit 80C51 microcontrollers. There are two working modes of the DQ80251: BINARY (where original 80C51 compiled code is executed) and SOURCE (native 80C251 mode, using all DQ80251 performance). DQ80251 has built-in, configurable DoCD-JTAG on chip debugger, supporting Keil DK251 and standalone DoCD debug software. Dhrystone 2.1 benchmark program runs 56.8 times faster than the original 80C51 and 4.81 times faster, than the original 80C251 at the same frequency. This performance can be also exploited to great advantage in low power applications, where the core can be clocked over fifty times slower, than the original implementation, for no performance penalty. Additionally, compiled code size for SOURCE mode is about 2 times smaller, comparing to identical standard 8051 code, since DQ80251 instructions are more effective.

The DQ80251 is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's 80251 Core has built in support for the DCD Hardware Debug System, called DoCD^TM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger

Family summary

Design	Dhry speed	on-chip CODE RAM/ROM	off-chip CODE	CODE write	IDATA space	XDATA space	XDATA, CODE wait states	DoCD^TM	PMU	Interrupt sources	DPTR	Timers	UART	IO Ports	Compare/ Capture	Watchdog	MDU MDU32	DI2CM	DI2CS	DSPI	DFPMU	DMAC	DCAN
DQ80251	56.8	8M	8M	+	1k-32k	8M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DQ8051CPU	25.13	64k/64k	64k/8M	+	256	16M	+	+	+	2	1	-	-	-	-	-	-	-	-	-	-	-	-
DQ8051	25.13	64k/64k	64k/8M	+	256	16M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DQ8051XP	26.62	64k/64k	64k/8M	+	256	16M	+	+	+	15	2	3	2	4	+	+	+	+	+	+	+	+	+
DP8051CPU	15.55	64k/64k	64k/8M	+	256	16M	+	+	+	2	1	-	-	-	-	-	-	-	-	-	-	-	-
DP8051	15.55	64k/64k	64k/8M	+	256	16M	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DP8051XP	15.55	64k/64k	64k/8M	+	256	16M	+	+	+	15	2	3	2	4	+	+	+	+	+	+	+	+	+
DP80C51	11.4	64k/64k	64k	+	256	64k	+	+	+	5	1	2	1	4	-	-	-	-	-	-	-	-	-
DT8051	8.1	64k/64k	64k	+	256	64k	-	+	+	11	1	2	1	1	-	-	-	-	-	-	-	-	-

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation device	Speed grade	Area Min [gates]	Area Full [gates]	Top frequency [MHz]
0,18 um	typical	15 100	28 600	120
0,13 um	typical	15 000	28 000	200
0,09 um	typical	14 500	26 100	300

DQ80251 core area and performance in ASIC devices - results given for working system with connected CODE and DATA memories. All CPU features and Peripherals have been included. DoCD JTAG debugger increases core size by approximately 3 000 gates.

CPU Features

100% binary compatible with industry standard 80C251, implementing BINARY and SOURCE modes
Single clock period per most of instructions
Quad-Pipelined architecture enables to run 56.8 times faster than the original 80C51 and 4.81 times faster, than 80C251 at the same frequency
Up to 53.411 VAX MIPS at 100 MHz
Up to 8M bytes of Program Memory
Up to 32k bytes of internal (on-chip) Data Memory
Up to 8M bytes of external (off-chip) Data Memory
Up to 16 MB of total memory space for CODE and DATA
64k bytes of extended stack space
User programmable Program Memory Wait States solution - for wide range of memories' speed
User programmable Extended Data Memory Wait States solution - for wide range of memories' speed
De-multiplexed Address/Data bus, to allow easy connection to memory
Full Program Memory writes
Interface for additional Special Function Registers
Fully synthesizable
Static synchronous design
No internal tri-states
Scan test ready

Symbol

idmdatai

idmdatao

idmaddr

idmoe

idmwe

gate0

gate1

rxd0i

rxd0o

txd0

xdmdatai

xdmready

xdmdatao

xdmdataz

xdmaddr

xdmbe

xdmrd

xdmwr

xdmce

int0

int1

prgdatai

prgready

prgdatao

prgdataz

prgaddr

prgbe

prgrd

prgwr

sfrdatai

sfrdatao

sfrraddr

sfrwaddr

sfroe

sfrwe

tdi

tck

tms

tdo

rtck

debugacs

coderun

port0i

port1i

port2i

port3i

port0o

port1o

port2o

port3o

stop

pmm

Pins description

Pin	Type	Description
idmdatai	input	Data bus from IDATA memory
t0	input	Timer 0 input
t1	input	Timer 1 input
gate0	input	Timer 0 gate input
gate1	input	Timer 1 gate input
rxd0i	input	Serial receiver input 0
xdmdatai	input	Data bus from EDATA Memory
xdmready	input	EDATA memory data ready
int0	input	External interrupt 0
int1	input	External interrupt 1
prgdatai	input	Data bus from CODE Memory
prgready	input	CODE memory data ready
sfrdatai	input	Data bus from user SFR"s
tdi	input	DoCD^TM TAP data input
tck	input	DoCD^TM TAP clock input
tms	input	DoCD^TM mode select input
port0i	input	Port 0 input
port1i	input	Port 1 input
port2i	input	Port 2 input
port3i	input	Port 3 input
idmdatao	output	Data bus for IDATA memory
idmaddr	output	IDATA Memory address bus
idmoe	output	Internal data memory output enable
idmwe	output	Internal data memory write enable
rxd0o	output	Serial receiver output 0
txd0	output	Serial transmitter output 0
xdmdatao	output	Data bus for EDATA memories
xdmdataz	output	Turn EDATA bus into "Z" state
xdmaddr	output	Address bus for EDATA memory
xdmbe	output	EDATA data bus byte enable
xdmrd	output	Extended data memory read
xdmwr	output	Extended data memory write
xdmce	output	Extended data memory chip enable
prgdatao	output	Data bus for CODE memory
prgdataz	output	Turn CODE bus into "Z" state
prgaddr	output	CODE memory address bus
prgbe	output	CODE data bus byte enable
prgrd	output	CODE memory read
prgwr	output	CODE memory write
sfrdatao	output	Data bus for user SFR"s
sfrraddr	output	Read address bus for user SFR"s
sfrwaddr	output	Write address bus for user SFR"s
sfroe	output	User SFR"s read enable
sfrwe	output	User SFR"s write enable
tdo	output	DoCD^TM TAP data output
rtck	output	DoCD^TM return clock line
debugacs	output	DoCD^TM accessing data
coderun	output	CPU is executing an instruction
port0o	output	Port 0 output
port1o	output	Port 1 output
port2o	output	Port 2 output
port3o	output	Port 3 output
stop	output	Stop mode indicator
pmm	output	Power management mode indicator

Block Diagram

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.

Control UnitPerforms the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.

Internal Data Memory InterfaceInternal Data Memory interface controls access into the whole 32kB of IDATA memory. It contains 16-bit Stack Pointer (SP) register and related logic. It is fully configurable from 1 kB to 32 kB.

idmdatai

idmdatao

idmaddr

idmoe

idmwe

REGFILEContains complete set of 80251 dedicated: 8-bit {R0, R1, ..., R15} registers, 16-bit {WR0, WR2, ..., WR30} and 32-bit {DR0, DR4, ..., DR28, DR56, DR60} registers.

TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

gate0

gate1

UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).

rxd0i

rxd0o

txd0

ALU16/32-bit Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW, PSW1), (B) registers and related logic, such as arithmetic unit, logic unit, multiplier and divider.

EDATA Memory InterfaceContains memory access related registers. It performs the Extended Data Memory (EDATA) addressing and data transfers. EDATA read/write cycle length can be programmed by user. EDATA covers also XDATA space from 80C51. This feature is called EDATA Memory Wait States and allows core to work with different speed memories. It is fully configurable. It works with synchronous or asynchronous memories.

xdmdatai

xdmready

xdmdatao

xdmdataz

xdmaddr

xdmbe

xdmrd

xdmwr

xdmce

Interrupt ControllerFour Levels interrupt control module is responsible for the interrupt manage system, for external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IPH, IPL) and (TCON) registers. Its upgraded version can be extended by extra user's dedicated interrupt sources. Interrupt vectors locations and spacing are fully configurable.

int0

int1

Program Memory InterfaceContains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory (CODE) can be also written. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. It works with synchronous or asynchronous memories.

prgdatai

prgready

prgdatao

prgdataz

prgaddr

prgbe

prgrd

prgwr

SFRs InterfaceSpecial Function Registers interface - controls access to the special registers. It contains standard and used defined registers and related logic. All SFR registers are bit addressable. User defined external devices can be quickly accessed (read, written or modified), by the use of direct addressing mode instructions.

sfrdatai

sfrdatao

sfrraddr

sfrwaddr

sfroe

sfrwe

DoCD^TM Debug UnitIt is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external data, program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, REGFILE and also on SFRs. Hardware breakpoint is executed, if any write/read occurrs at particular address, with certain data pattern or without pattern. Two additional pins - CODERUN and DEBUGACS, indicate the sate of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCD^TM debugger. The DoCD^TM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.

tdi

tck

tms

tdo

rtck

debugacs

coderun

ALUArithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.

I/O portsBlock contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3

port0i

port1i

port2i

port3i

port0o

port1o

port2o

port3o

Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.

stop

pmm

Data bus Internal data bus

SFR bus Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Internal data bus 8-bit internal data bus

Units

Opcode Decoder

Performs an opcode decoding instruction and control functions for all other blocks.

Control Unit

Performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages the execution of all microcontroller tasks.

Internal Data Memory Interface

Internal Data Memory interface controls access into the whole 32kB of IDATA memory. It contains 16-bit Stack Pointer (SP) register and related logic. It is fully configurable from 1 kB to 32 kB.

REGFILE

Contains complete set of 80251 dedicated: 8-bit {R0, R1, ..., R15} registers, 16-bit {WR0, WR2, ..., WR30} and 32-bit {DR0, DR4, ..., DR28, DR56, DR60} registers.

Timers

System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

UART0

Universal Asynchronous Receiver and Transmitter module is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of the second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).

ALU

16/32-bit Arithmetic Logic Unit performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW, PSW1), (B) registers and related logic, such as arithmetic unit, logic unit, multiplier and divider.

EDATA Memory Interface

Contains memory access related registers. It performs the Extended Data Memory (EDATA) addressing and data transfers. EDATA read/write cycle length can be programmed by user. EDATA covers also XDATA space from 80C51. This feature is called EDATA Memory Wait States and allows core to work with different speed memories. It is fully configurable. It works with synchronous or asynchronous memories.

Interrupt Controller

Four Levels interrupt control module is responsible for the interrupt manage system, for external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IPH, IPL) and (TCON) registers. Its upgraded version can be extended by extra user's dedicated interrupt sources. Interrupt vectors locations and spacing are fully configurable.

Program Memory Interface

Contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory (CODE) can be also written. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories. It works with synchronous or asynchronous memories.

SFRs Interface

Special Function Registers interface - controls access to the special registers. It contains standard and used defined registers and related logic. All SFR registers are bit addressable. User defined external devices can be quickly accessed (read, written or modified), by the use of direct addressing mode instructions.

DoCD^TM Debug Unit

It is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external data, program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, REGFILE and also on SFRs. Hardware breakpoint is executed, if any write/read occurrs at particular address, with certain data pattern or without pattern. Two additional pins - CODERUN and DEBUGACS, indicate the sate of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCD^TM debugger. The DoCD^TM system includes JTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.

ALU

Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.

I/O ports

Block contains 8051 general purpose I/O ports. Each of ports pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3

ALU

Power Management Unit

Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It's highly desirable, when microcontroller is planned to be used in portable and power critical applications.