Digital Core Design

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DT8051

Tiny Area High Performance Microcontroller

The DT8051 is an area optimized, tiny soft core of a single-chip 8-bit embedded microcontroller, based on the World's fastest and most popular DP8051 core, available since over 8 years. The DT8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. It has a very low gate count architecture, giving 6 650 ASIC gates for the complete system, including DoCD on-chip debugger. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. The DT8051 includes a 2-wire DoCD on-chip debugger (TTAGTM), up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface for external SFR. The DT8051 Core has a built-in support for the 2-wire TTAGTM interface - DCD Hardware Debug System, called DoCDTM. This version of the debugger is dedicated for applications, where a number of external pins is limited.

The DT8051 is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow.

Each of DCD's 8051 Cores has a built-in support for the DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, set breakpoints, watchpoints, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger

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Family summary

 

Design Dhry
speed
on-chip
CODE
RAM/ROM
off-chip
CODE
CODE
write
IDATA
space
XDATA
space
XDATA,
CODE
wait states
DoCDTM PMU Interrupt
sources
DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DQ80251 75.08 8M 8M + 1k-32k 8M + + +  15 1 3 2 4 + + + + + + + + +
DQ8051CPU 28.40 64k/64k 64k/8M + 256 16M + + +  2 2 - - - - - - - - - - - -
DQ8051 29.01 64k/64k 64k/8M + 256 16M + + +  5 2 2 1 4 - - - - - - - - -
DQ8051XP 29.01 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP8051CPU 15.36 64k/64k 64k/8M + 256 16M + + +  2 1 - - - - - - - - - - - -
DP8051 15.36 64k/64k 64k/8M + 256 16M + + +  5 1 2 1 4 - - - - - - - - -
DP8051XP 15.55 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP80C51 11.46 64k/64k 64k + 256 64k + + +  5 1 2 1 4 - - - - - - - - -
DT8051 8.11 64k/64k 64k + 256 64k - + + 11 1 2 1 1 - - - - - - - - -

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation Speed
grade
Utilized Area
[gates]
Frequency
[MHz]
0.25u area typical 6 0000 / 7 5301 1000 / 1001
0.18u area typical 5 7200 / 7 1501 1300 / 1301
0.09u area typical 5 6000 / 6 6501 2300 / 2301

DT8051 without0 and with1 DoCD TTAG debugger - implementation results for ASIC devices. Results given for working system, with connected SFR, IDATA, CODE and XDATA memories.

0 - no DoCD debugger  1 - compact DoCD version, includes processor execution control (run, halt, reset, step); read-write all processor content (PC, SFRs); read-write all processor memories (IDATA, XDATA, CODE memory); FLASH code memory programming; one hardware code execution breakpoint; unlimited number of OPCODE execution breakpoints

Implementation Speed
grade
Utilized Area Frequency
[MHz]
SPARTAN-3E -5 10290 / 11721 Slices   750 /   751
VIRTEX-IIP -7 10260 / 11741 Slices 1300 / 1301
VIRTEX-4 -11 10310 / 11771 Slices 1400 / 1401
VIRTEX-5 -3 5790 /   6251 Slices  2000 / 2001

DT8051 without0 and with1 DoCD TTAG debugger - implementation results for XILINX devices. Results given for working system, with connected SFR, IDATA, CODE and XDATA memories.

0 - no DoCD debugger  1 - compact DoCD version, includes processor execution control (run, halt, reset, step); read-write all processor content (PC, SFRs); read-write all processor memories (IDATA, XDATA, CODE memory); FLASH code memory programming; one hardware code execution breakpoint; unlimited number of OPCODE execution breakpoints

Implementation Speed
grade
Utilized Area Frequency
[MHz]
CYCLONE-II -6 16660 / 19131    LC    950 /   901
CYCLONE-III -6 16560 / 19111    LC  1000 /  951
STRATIX-II -3 12870 / 15071 ALUT 1550 / 1501
STRATIX-III -2 12890 / 15081 ALUT  2100 / 2001

DT8051 without0 and with1 DoCD TTAG debugger - implementation results for ALTERA devices. Results given for working system, with connected SFR, IDATA, CODE and XDATA memories.

0 - no DoCD debugger  1 - compact DoCD version, includes processor execution control (run, halt, reset, step); read-write all processor content (PC, SFRs); read-write all processor memories (IDATA, XDATA, CODE memory); FLASH code memory programming; one hardware code execution breakpoint; unlimited number of OPCODE execution breakpoints


CPU Features


Symbol

 reset
 clk
 xdatai (7:0)
xdatao (7:0) 
xdataz 
xaddress (15:0) 
xdatard 
xdatawr 
xprgrd 
xprgwr 
 port2i (7:0)
port2o (7:0) 
 int0
 int1
 int2
 int3
 int4
 int5
 int6
 int7
 prgdatai (7:0)
prgdatao (7:0) 
prgaddr (15:0) 
prgramwr 
 sfrdatai (7:0)
sfrdatao (7:0) 
sfrwe 
sfroe 
sfraddr (6:0) 
 rxd0i
txd0 
 ttdi
ttdo 
ttdoen 
ttck 
 t0
 t1
 gate0
 gate1
stop 
pmm 
 ramdatai (7:0)
ramdatao (7:0) 
ramaddr (7:0) 
ramoe 
ramwe 

Pins description

PinTypeDescription
resetinputGlobal reset
clkinputGlobal clock
xdatai (7:0)inputData bus from external data/code memory
port2i (7:0)inputPort 2 input
int0inputExternal interrupt 0
int1inputExternal interrupt 1
int2inputExternal interrupt 2
int3inputExternal interrupt 3
int4inputExternal interrupt 4
int5inputExternal interrupt 5
int6inputExternal interrupt 6
int7inputExternal interrupt 7
prgdatai (7:0)inputData bus from internal program memory
sfrdatai (7:0)inputData bus from user SFRs
rxd0iinputSerial receiver input 0
ttdiinputDoCDTM data input
t0inputTimer 0 input
t1inputTimer 1 input
gate0inputTimer 0 gate input
gate1inputTimer 1 gate input
ramdatai (7:0)inputData bus from internal data memory
xdatao (7:0)outputData bus for external data/code memory
xdatazoutputExternal XDATA bus "Z" state
xaddress (15:0)outputExternal data/code memory address bus
xdatardoutputExternal data memory read
xdatawroutputExternal data memory write
xprgrdoutputExternal Program Memory read
xprgwroutputExternal Program Memory write
port2o (7:0)outputPort 2 output
prgdatao (7:0)outputOutput data bus for Internal Program Memory
prgaddr (15:0)outputInternal Program memory address bus
prgramwroutputInternal Program Memory write
sfrdatao (7:0)outputData bus for user SFRs
sfrweoutputUser SFRs write enable
sfroeoutputUser SFRs read
sfraddr (6:0)outputUser SFRs address bus
txd0outputSerial transmitter output 0
ttdooutputDoCDTM data output
ttdoenoutputDoCDTM data output enable
ttckoutputDoCDTM data clock
stopoutputStop mode indicator
pmmoutputPower management mode indicator
ramdatao (7:0)outputData bus for internal data memory
ramaddr (7:0)outputRAM address bus
ramoeoutputInternal data memory read
ramweoutputInternal data memory write enable

Block Diagram

Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.
Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
External Memory InterfaceContains memory access related registers, like Data Page High (DPH) and Data Page Low (DPL) registers. It performs the memory addressing and data transfers.
xdatai (7:0)
xdatao (7:0)
xdataz
xaddress (15:0)
xdatard
xdatawr
xprgrd
xprgwr
I/O PortsBlock contains 8051's general purpose I/O ports. Each of port's pin can be read/write as a single bit or as an 8-bit bus.
port2i (7:0)
port2o (7:0)
Interrupt ControllerInterrupt Control module is responsible for the interrupt manage system for the eight external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.
int0
int1
int2
int3
int4
int5
int6
int7
Program Memory InterfaceIt contains Program Counter (PC) and related logic. It performs the instructions code fetching. Whole program memory (FLASH or SRAM type), can be written by DoCD™ debugger or application can modify some part of its code - for example, storing some data which shouldn't volatile.
prgdatai (7:0)
prgdatao (7:0)
prgaddr (15:0)
prgramwr
SFRs InterfaceSpecial Function Registers interface - controls access to externally connected peripherals, through SFR bus.
sfrdatai (7:0)
sfrdatao (7:0)
sfrwe
sfroe
sfraddr (6:0)
UART0Universal Asynchronous Receiver and Transmitter module. It is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0, loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 2 asynchronous modes, with variable baudrate, covering all standard transmission speeds.
rxd0i
txd0
DoCDTM TTAGDoCDTM Debug Unit, 2-wire, low gate count, real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints control execution of program memory code; hardware watchpoints can be set and control internal and external data memories and SFRs. Hardware watchpoints are executed if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins (CODERUN and DEBUGACS) indicate the sate of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core, in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
Please note that TTDI, TTDO, TTDOEN pins are connected together as a single bidirectional pin, called TTDIO
ttdi
ttdo
ttdoen
ttck
TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
t0
t1
gate0
gate1
Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.
stop
pmm
Internal Data Memory InterfaceInterface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
ramdatao (7:0)
ramaddr (7:0)
ramdatai (7:0)
ramoe
ramwe
ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.
reset
clk
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.
Internal data bus 8-bit internal data bus

Units

Control Unit
It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.
Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
External Memory Interface
Contains memory access related registers, like Data Page High (DPH) and Data Page Low (DPL) registers. It performs the memory addressing and data transfers.

I/O Ports
Block contains 8051's general purpose I/O ports. Each of port's pin can be read/write as a single bit or as an 8-bit bus.
Interrupt Controller
Interrupt Control module is responsible for the interrupt manage system for the eight external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.
Program Memory Interface
It contains Program Counter (PC) and related logic. It performs the instructions code fetching. Whole program memory (FLASH or SRAM type), can be written by DoCD™ debugger or application can modify some part of its code - for example, storing some data which shouldn't volatile.

SFRs Interface
Special Function Registers interface - controls access to externally connected peripherals, through SFR bus.
UART0
Universal Asynchronous Receiver and Transmitter module. It is full duplex, which means, that it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0, loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 2 asynchronous modes, with variable baudrate, covering all standard transmission speeds.
DoCDTM TTAG
DoCDTM Debug Unit, 2-wire, low gate count, real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints control execution of program memory code; hardware watchpoints can be set and control internal and external data memories and SFRs. Hardware watchpoints are executed if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins (CODERUN and DEBUGACS) indicate the sate of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core, in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
Please note that TTDI, TTDO, TTDOEN pins are connected together as a single bidirectional pin, called TTDIO

Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.
Internal Data Memory Interface
Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

ALU
Arithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.