Digital Core Design

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DP8051

Pipelined High Performance Microcontroller

The DP8051 is an ultra high performance, speed optimized soft core, of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management PMU unit.
The DP8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of DP8051: Harvard, where internal data and program buses are separated and von Neumann, with common program and external data bus. The DP8051 has a Pipelined RISC architecture and executes 120-300 million instructions per second. Dhrystone 2.1 benchmark program runs from 11.46 to 15.55 times faster, than the original 80C51 at the same frequency. The same C compiler was used for benchmarking of the core vs 80C51, with the same settings. This performance can also be exploited to great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion.

The DP8051 is delivered with fully automated testbench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's 8051 Core has built-in support for the DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. More details about DCD on Chip Debugger


Family summary

 

Design Dhry
speed
on-chip
CODE
RAM/ROM
off-chip
CODE
CODE
write
IDATA
space
XDATA
space
XDATA,
CODE
wait states
DoCDTM PMU Interrupt
sources
DPTR Timers UART IO Ports Compare/
Capture
Watchdog MDU
MDU32
DI2CM DI2CS DSPI DFPMU DMAC DCAN
DQ80251 75.08 8M 8M + 1k-32k 8M + + +  15 1 3 2 4 + + + + + + + + +
DQ8051CPU 28.40 64k/64k 64k/8M + 256 16M + + +  2 2 - - - - - - - - - - - -
DQ8051 29.01 64k/64k 64k/8M + 256 16M + + +  5 2 2 1 4 - - - - - - - - -
DQ8051XP 29.01 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP8051CPU 15.36 64k/64k 64k/8M + 256 16M + + +  2 1 - - - - - - - - - - - -
DP8051 15.36 64k/64k 64k/8M + 256 16M + + +  5 1 2 1 4 - - - - - - - - -
DP8051XP 15.55 64k/64k 64k/8M + 256 16M + + + 15 2 3 2 4 + + + + + + + + +
DP80C51 11.46 64k/64k 64k + 256 64k + + +  5 1 2 1 4 - - - - - - - - -
DT8051 8.11 64k/64k 64k + 256 64k - + + 11 1 2 1 1 - - - - - - - - -

The main features of each DCD's DQ8051, DQ80251, DP8051, DP80C51, DT8051 family member have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below. . 

Implementation Speed
grade
Utilized Area
[gates]
Frequency
[MHz]
0.25u area typical 8 100 100
0.25u speed typical 9 600 250
0.18u area typical 7 650 100
0.18u speed typical 9 000 300

DP8051 implementation results for ASIC devices - results given for working system, with connected IDATA, CODE and XDATA memories. The CPU features and Peripherals have been included. DoCD TTAG debugger increases core size by approximately 1 800 gates.  

Implementation Speed
grade
Utilized Area
[gates]
Frequency
[MHz]
XP -5 2430 LUT4s 74
EC -5 2430 LUT4s 80
ECP -5 2500 LUT4s  86
XP2 -7 2350 LUT4s  98
ECP2 -7 2350 LUT4s  120
ECP2M -7 2350 LUT4s  123
SC -7 2470 LUT4s 149

DP8051 implementation results for LATTICE devices - results given for working system, with connected IDATA, CODE and XDATA memories. The CPU features and Peripherals have been included.


Implementation Speed
grade
Utilized Area  Frequency
[MHz]
SPARTAN-II -6 1100 Slices 53
SPARTAN-IIE -7 1100 Slices 64
SPARTAN-III -5 1100 Slices  73
VIRTEX-II -6  1100 Slices 99
VIRTEX-II pro -7 1100 Slices 123
VIRTEX-4 -11 1100 Slices 107
VIRTEX-5 -3  1699 LCells 200

DP8051 implementation results for XILINX devices - results given for working system, with connected IDATA, CODE and XDATA memories. The CPU features and Peripherals have been included. 

Implementation Speed
grade
Utilized Area
 [LC]
Frequency
[MHz]
CYCLONE-II -6 2250 LC 93
CYCLONE-III -6 2400 LC 111
Arria GX -6 1595 ALUT 112
STRATIX-II -3 1580 ALUT 160
STRATIX-III -2 1580 ALUT 191
STRATIX-IV -2 1580 ALUT 196

DP8051 implementation results for ALTERA devices - results given for working system, with connected IDATA, CODE and XDATA memories. The CPU features and Peripherals have been included. 


CPU Features


Symbol

 reset
 clk
 iprgramsize (2:0)
 iprgromsize (2:0)
 rxd0i
rxd0o 
txd0 
 t0
 t1
 gate0
 gate1
 port0i (7:0)
 port1i (7:0)
 port2i (7:0)
 port3i (7:0)
port0o (7:0) 
port1o (7:0) 
port2o (7:0) 
port3o (7:0) 
 ramdatai (7:0)
ramdatao (7:0) 
ramaddr (7:0) 
ramoe 
ramwe 
 int0
 int1
 sfrdatai (7:0)
sfrdatao (7:0) 
sfrwe 
sfroe 
sfraddr (6:0) 
 prgramdata (7:0)
 prgromdata (7:0)
prgaddr (15:0) 
prgdatao (7:0) 
prgramwr 
 xdatai (7:0)
 ready
xdatao (7:0) 
xdataz 
xaddr (23:0) 
xprgrd 
xprgwr 
xdatard 
xdatawr 
stop 
pmm 
 tdi
 tck
 tms
tdo 
rtck 
 sxdmdatai (7:0)
sxdmaddr (15:0) 
sxdmdatao (7:0) 
sxdmoe 
sxdmwe 

Pins description

PinTypeDescription
resetinputGlobal reset
clkinputGlobal clock
iprgramsize (2:0)inputSize of on-chip RAM CODE
iprgromsize (2:0)inputSize of on-chip ROM CODE
rxd0iinputSerial receiver input 0
t0inputTimer 0 input
t1inputTimer 1 input
gate0inputTimer 0 gate input
gate1inputTimer 1 gate input
port0i (7:0)inputPort 0 input
port1i (7:0)inputPort 1 input
port2i (7:0)inputPort 2 input
port3i (7:0)inputPort 3 input
ramdatai (7:0)inputData bus from internal data memory
int0inputExternal interrupt 0
int1inputExternal interrupt 1
sfrdatai (7:0)inputData bus from user SFRs
prgramdata (7:0)inputData bus from internal RAM program memory
prgromdata (7:0)inputData bus from internal ROM program memory
xdatai (7:0)inputData bus from external memories
readyinputExternal memory data ready
tdiinputDoCDTM TAP data input
tckinputDoCDTM TAP clock line
tmsinputDoCDTM TAP mode select
sxdmdatai (7:0)inputData bus from sync external data memory (SXDM)
rxd0ooutputSerial receiver output 0
txd0outputSerial transmitter output 0
port0o (7:0)outputPort 0 output
port1o (7:0)outputPort 1 output
port2o (7:0)outputPort 2 output
port3o (7:0)outputPort 3 output
ramdatao (7:0)outputData bus for internal data memory
ramaddr (7:0)outputRAM address bus
ramoeoutputInternal data memory read
ramweoutputInternal data memory write enable
sfrdatao (7:0)outputData bus for user SFRs
sfrweoutputUser SFRs write enable
sfroeoutputUser SFRs read
sfraddr (6:0)outputUser SFRs address bus
prgaddr (15:0)outputInternal program memory address bus
prgdatao (7:0)outputData bus for internal program memory
prgramwroutputInternal program memory write
xdatao (7:0)outputData bus for external memories
xdatazoutputTurn xdata bus into "Z" state
xaddr (23:0)outputAddress bus for external memories
xprgrdoutputExternal program memory read
xprgwroutputExternal program memory write
xdatardoutputExternal data memory read
xdatawroutputExternal data memory write
stopoutputStop mode indicator
pmmoutputPower management mode indicator
tdooutputDoCDTM TAP data output
rtckoutputDoCDTM return clock
sxdmaddr (15:0)outputSync XDATA memory address bus (SXDM)
sxdmdatao (7:0)outputData bus for Sync XDATA memory (SXDM)
sxdmoeoutputSync XDATA memory read (SXDM)
sxdmweoutputSync XDATA memory write (SXDM)

Block Diagram

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.
Control UnitIt performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages execution of all microcontroller tasks.
iprgramsize (2:0)
iprgromsize (2:0)
UART0Universal Asynchronous Receiver and Transmitter module is full duplex, which means, it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in the system).
rxd0i
rxd0o
txd0
TimersSystem timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
t0
t1
gate0
gate1
ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.
I/O PortsBlock contains 8051's general purpose I/O ports. Each of the port's pin can be read/written as a single bit or as a 8-bit bus P0, P1, P2, P3.
port0i (7:0)
port1i (7:0)
port2i (7:0)
port3i (7:0)
port0o (7:0)
port1o (7:0)
port2o (7:0)
port3o (7:0)
Internal Data Memory InterfaceInterface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
ramdatao (7:0)
ramaddr (7:0)
ramdatai (7:0)
ramoe
ramwe
Interrupt ControllerInterrupt Controller module is responsible for the interrupt manage system of the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.
int0
int1
SFRs InterfaceSpecial Function Registers interface - controls access to externally connected peripherals, through SFR bus.
sfrdatai (7:0)
sfrdatao (7:0)
sfrwe
sfroe
sfraddr (6:0)
Program Memory InterfaceProgram Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.
prgramdata (7:0)
prgromdata (7:0)
prgaddr (15:0)
prgdatao (7:0)
prgramwr
External Memory InterfaceContains memory access related registers, such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by the user. This feature is called Program Memory Wait States and it allows core, to work with different speed program memories.
xdatai (7:0)
xdatao (7:0)
xdataz
xaddr (23:0)
ready
xprgrd
xprgwr
xdatard
xdatawr
Power Management UnitPower Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.
stop
pmm
DoCDTM TTAG DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
tdi
tck
tms
tdo
rtck
SXDM interfaceSynchronous eXternal Data Memory (SXDM) Interface – contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.
sxdmdatai (7:0)
sxdmaddr (15:0)
sxdmdatao (7:0)
sxdmoe
sxdmwe
reset
clk
SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.
Internal data bus 8-bit internal data bus

Units

Opcode Decoder
Performs an opcode decoding instruction and control functions for all other blocks.
Control Unit
It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and it manages execution of all microcontroller tasks.
UART0
Universal Asynchronous Receiver and Transmitter module is full duplex, which means, it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning, it can commence reception of a second byte, before the previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register and reading SBUF0, reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in the system).

Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 (or 4) CLK periods, when appropriate timer is enabled. In the counter mode, the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.
ALU
Arithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic, like arithmetic unit, logic unit, multiplier and divider.
I/O Ports
Block contains 8051's general purpose I/O ports. Each of the port's pin can be read/written as a single bit or as a 8-bit bus P0, P1, P2, P3.

Internal Data Memory Interface
Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.
Interrupt Controller
Interrupt Controller module is responsible for the interrupt manage system of the external and internal interrupt sources. It contains interrupt related registers, such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.
SFRs Interface
Special Function Registers interface - controls access to externally connected peripherals, through SFR bus.

Program Memory Interface
Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader, to load new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.
External Memory Interface
Contains memory access related registers, such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by the user. This feature is called Program Memory Wait States and it allows core, to work with different speed program memories.
Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode), to significantly reduce power consumption. Switchback feature allows UARTs and interrupts to be processed in full speed mode, if enabled. It is highly desirable, when microcontroller is planned to be used in portable and power critical applications.

DoCDTM TTAG
DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware watchpoints can be set and controlled on internal and external data memories and also on SFRs. Hardware watchpoints are executed, if any write/read occurs at particular address, with certain data pattern or without pattern. Two additional pins: CODERUN and DEBUGACS, indicate the state of the debugger and CPU. CODERUN is active, when CPU is executing an instruction. DEBUGACS pin is active, when any access is performed by DoCDTM debugger. The DoCDTM system includes TTAG interface and complete set of tools, to communicate and work with core in real time debugging. It is built, as a scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
SXDM interface
Synchronous eXternal Data Memory (SXDM) Interface – contains XDATA memory access related logic, allowing fast access to synchronous memory devices. It performs the external Data Memory addressing and data transfers. This memory can be used to store large variables, frequently accessed by CPU, improving overall performance of application.