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Family summary

The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

• Cycle compatible with original implementation
• Software compatible with 68HC11K industry standard
• I/O Wrapper, making it pin-compatible core
• SFR registers remapped to any 4KB memory page
• Two power saving modes: STOP, WAI
• Fully synthesizable
• Static synchronous design
• No internal tri-states
• Scan test ready

Symbol

 clk

 rst

 cmf

 adcdatai

adcdatao 

adcclock 

adccs 

rw 

 moda_lir

 modb

e 

 xirq

 irq

 porta

 portc

 portd

 porte (7:0)

 portg

 porth

 portj*

 portk*

portb (7:0) 

portf (7:0) 

 docddatai

 clkdocd

docddatao 

docdclk 

 esi

eso 

esck 

ecs 

ADC ControllerThe ADCCTRL used in D68HC11, provides communication between the internal ADC related registers and program running on D68HC11 and external ADC converter. Supports several Parallel and serial ADC.

adcdatai

adcdatao

adcclock

adccs

BUSCTRLBus Controller - manages data exchange between CPU and several Internal and External Memories

rw

COPCOP Watchdog Timer

CTRLUNITPerforms the core synchronization and data flow control. This module manages execution of all instructions.

moda_lir

modb

e

Interrupt ControllerD68HC11 has implemented 17-level interrupt priority control. External interrupt pins are activated at low level (XIRQ, IRQ pins) or falling edge (IRQ pin). External interrupt requests by IRQ and XIRQ, are sampled each 1 system clock at the rising edge of CLK. The D68HC11 peripheral systems generate maskable interrupts, which are recognized only, if the global interrupt mask bit (I) in the CCR, is cleared. Maskable interrupts are prioritized according to default arrangement (look at the table below), established during reset. However, any source may be elevated to the highest maskable priority position, by using HPRIO register. When interrupt condition occurs, an interrupt status flag is set to indicate the condition.

xirq

irq

PULSEACCAThis system is based on an 8-bit counter and can be configured to operate as a simple event counter or as a tool for gated time accumulation. Unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). Control bits allow the user to configure and control the pulse accumulator subsystem. Two maskable interrupts are associated with the system, each having its own controls and interrupt vector. The PAI pin associated with the pulse accumulator, can be configured to act as a clock (event counting mode) or as a gate signal, to enable a free-running of E divided by 64 clock, to the 8-bit counter (gated time accumulation mode). The alternate functions of the PAI (Pulse Accumulator Input) pin, present some interesting application possibilities.

SCIThe SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore, the differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and major logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. The logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, which can be used in applications with a modem.

SPIIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of Serial Clock Signal (SCK). It enables the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor communications, in a multi-master system. The Serial Clock Line (SCK) synchronizes shifting and sampling of the information, on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data rates are as high, as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector, automatically disables SPI output drivers, if more than one SPI devices simultaneously attempt to become a bus master.

TIMERMain Timer system, including Compare, Capture and Real Time Interrupt logic. This timer system is based on a free-running, 16-bit counter, with a 4-stage programmable prescaler. A timer overflow function allows software, to extend the timing capability of the system, beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time, when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals, or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in more detail. A programmable periodic interrupt circuit (RTI) is tapped off the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer, in which the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain. The timer subsystem involves more registers and control bits, than any other subsystem on the MCU. Each of the three input-capture functions, has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions, has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit the software, to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications, although it is not as efficient as a dedicated hardware, for some specific timing applications.

Chip Select UnitControls four external chip select signals: GPCS1, GPCS2, CSPROG and CSIO.

IO PortsGeneral Purpose I/O Ports Shared with: Address and Data buses, and peripheral functions.

porta

portb (7:0)

portc

portd

porte (7:0)

portf (7:0)

portg

porth

portj*

portk*

MEUMEU (Memory Expansion Unit) with six address extension lines, allows up to (for example) sixteen 32K byte banks of external memory, to be addressed in either of two bank windows.

Timer 2*Timer 2 comprises a 4-stage prescaler and a 16-bit counter. It has three associated 16-bit output compare registers, along with a software-programmable input capture or output compare register. * available in D68HC11KW1 only

Timer 3*Timer 3 comprises a 4-stage prescaler and a 16-bit counter. It has three associated 16-bit output compare registers, along with a software-programmable input capture or output compare register. * available in D68HC11KW1 only

ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG) and related logic, such as arithmetic unit, logic unit, multiplier and divider.

DoCDTM DoCDTM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCDTM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off. The separate DoCDTM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).

docddatai

docddatao

docdclk

clkdocd

EEPROMCTRLExternal Serial EEPROM controller. This optional module, manages data exchange between D68HC11 and external EEPROM. During initialization, it copies contents of the whole external EEPROM, to internal EEPRAM (EEPROM Mirror implemented in standard parallel RAM). This module has several different options, therefore its details have been described in a separate document.

esi

eso

esck

ecs

clk

rst

cmf

SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Data bus Internal 8-bit data bus.

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