Digital Core Design

D68HC11F

8-bit Microcontrollers Family

Documentation

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Family Summary
Performance
Info
Pins description
Block diagram
Units

The D68HC11F is a synthesisable SOFT Microcontroller IP Core, fully compatible with the Motorola 68HC11F1 industry standard. It can be used as a direct replacement for the 68HC11F1 Microcontrollers.
In the standard configuration, the core has integrated on-chip major peripheral functions. An asynchronous serial communications interface (SCI) and separate synchronous serial peripheral interface (SPI) are included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem, can count external events or measure external periods. Self-monitoring on-chip circuitry is included to protect the D68HC11F against system errors. The Computer Operating Properly (COP) watchdog system, protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes - WAIT and STOP, are available to conserve additional power. These modes make the D68HC11F IP Core especially attractive for automotive and battery-driven applications.
The D68HC11F Microcontroller Core can be equipped with the ADC Cotroller, allowing use of external ADC Controller with standard ADC software. The ADC Controller makes external ADC's visible as internal ADC's in original 68HC11F1 Microcontrollers.
The D68HC11F has built-in, real time hardware on chip debugger - the DoCD^TM, allowing easy software debugging and validation.
The D68HC11F is fully customizable - it is delivered in the exact configuration to meet user's requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.

Each of the DCD's D68HC11F Core, has built-in support for DCD Hardware Debug System, called DoCD^TM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC).
Unlike other on-chip debuggers, the DoCD^TM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories. More details about DCD on Chip Debugger

Family summary

Family	IP Core	Architecture type	Memory space	DoCD^TM	UART (SCI)	SPI M/S	IO Ports	Watchdog Timer	Timer	Compare / Capture	Pulse accumulator	READY pin	Chip Selects	Gatecount
HC05, HC08	DF6805	fast	64k	+	+	-	4	+	1	2/2	-	+	-	7000
-	DF6808	fast	64k	+	+	-	4	+	1	2/2	-	+	-	8300
-	D68HC05	legacy	64k	+	+	+	4	+	1	1/1	-	-	-	-
-	D68HC08	legacy	64K	+	+	+	4	+	1	2/1	-	-	-	10000
HC11	DF6811E	fast	64k	+	+	+	5	+	1	5/4	+	+	-	12000
-	DF6811F	fast	64k	+	+	+	7	+	1	5/4	+	+	-	14000
-	DF6811K	fast	1M	+	+	+	10	+	3	13/6	+	+	-	21000
-	D68HC11E	legacy	64k	+	+	+	5	+	1	5/4	+	-	-	13000
-	D68HC11K	legacy	1M	+	+	1	10	+	3	13/6	+	-	4	21000
-	D68HC11F	legacy	64k	+	+	+	7	+	1	5/4	-	-	4	13500
6802, 6803	DF6802	fast	64k	+	-	-	-	-	-	-	-	-	-	-
-	DF6803	fast	64k	+	+	+	4	-	1	+	-	-	-	-
-	D6802	legacy	64k	+	-	-	-	-	-	-	-	-	-	3600
-	D6803	legacy	64k	+	+	+	4	-	1	+	-	-	-	6000

The main features of each D68XX and DF68XX family member, have been summarized in the table above. It gives a brief member characteristic, helping you to select the most suitable IP Core for your application. You can specify your own peripheral set (including listed above and the others) and request the core modifications.

Performance

Each core has been tested in variety of FPGA and ASIC technologies. Its implementation's results are summarized below.

Implementation	Speed grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-IIE	-7	2136	33
SPARTAN-III	-5	2135	41
SPARTAN-IIIE	-5	2135	43
VIRTEX-II	-6	2146	67
VIRTEX-IV	-12	2136	84

Implementation results of the D68HC11F1 in XILINX devices. All features are included.

Implementation	Speed grade	Utilized Area [LC]	Frequency [MHz]
FUSION	-2	7725	34
Axcelerator	-2	5198	39
ProASIC3	-2	7773	31
ProASIC3E	-2	7773	30

D68HC11 implementation results for ACTEL devices. All features have been included.

Implementation	Speed grade	Utilized Area [LC / ALUT]	Frequency [MHz]
CYCLONE	-6	3742	55
CYCLONE II	-6	3741	50
CYCLONE III	-6	3744	55
Cyclone IV	-6	3797	70
STRATIX	-5	3731	52
STRATIX II	-3	2540	86
STRATIX III	-2	2537	107
STRATIX IV	-2	2623	137

D68HC11F implementation results for ALTERA devices.

Implementation	Speed grade	Area [Slices]	Frequency [MHz]
XP	-	2155	47
XP2	-	2158	47
MachXO2	-	1736	34

D68HC11F implementation results for LATTICE devices.

CPU Features

Cycle compatible with original implementation
Software compatible with 68HC11 industry standard
I/O Wrapper making it pin-compatible core
SFR registers remapped to any 4KB memory page
Two power saving modes: STOP, WAI
Fully synthesizable
Static synchronous design
No internal tri-states
Scan test ready

Symbol

clk

rst

cmf

moda_lir

modb

xirq

irq

docddatai

clkdocd

docddatao

docdclk

porta

portc

portd

porte (7:0)

portg

portb (7:0)

portf (7:0)

adcdatai

adcdatao

adcclock

adccs

esi

eso

esck

ecs

Pins description

Pin	Type	Description
clk	input	Global clock
rst	input	Global reset
cmf	input	Clock monitor fail reset
moda_lir	input	MODA pin input shared with LIR output
modb	input	Mode B input
xirq	input	Non-maskable interrupt request
irq	input	Maskable interrupt request
docddatai	input	DoCD^TM serial data input
clkdocd	input	Clock signal to DoCD^TM On chip Debugger module. This separate clock line allow DoCD^TM to operate during the SLEEP mode (major clock CLK is stopped).
porta	input	8 Bit I/O shared with Main Timer syatem: Pulse Accumulator, and IC, OC lines
portc	input	GP I/O Port shared with Data Bus.
portd	input	GP I/O Port shared with SPI and SCI functions.
porte (7:0)	input	8-bit Input Port shared with ADC Controller - when enabled.
portg	input	GP I/O Port shared with Chip Select Unit
adcdatai	input	Serial ADC data input
esi	input	Serial Data input - connected to data output pin on EEPROM memory
e	output	E Clock output
docddatao	output	DoCD^TM serial data output
docdclk	output	DoCD^TM serial data clock line
portb (7:0)	output	8-Bit output port, shared with Address bus (15:8)
portf (7:0)	output	8-bit output port, shared with Address Bus - (7:0)
adcdatao	output	Serial ADC data output
adcclock	output	Serial clock to ADC devices
adccs	output	Serial ADC chip select line
eso	output	Serial data output - connected to data input on EEPROM Memory
esck	output	EEPROM SPI Clock line
ecs	output	EEPROM Chip Select

Block Diagram

CTRLUNITPerforms the core synchronization and data flow control. This module manages execution of all instructions.

moda_lir

modb

Interrupt ControllerD68HC11 has implemented 17-level interrupt priority control. External interrupt pins are activated at low level (XIRQ, IRQ pins) or falling edge (IRQ pin). External interrupt requests by IRQ and XIRQ, are sampled each 1 system clock at the rising edge of CLK. The D68HC11 peripheral systems generate maskable interrupts, which are recognized only, if the global interrupt mask bit (I) in the CCR, is cleared. Maskable interrupts are prioritized according to default arrangement (look at the table below), established during reset. However, any source may be elevated to the highest maskable priority position, by using HPRIO register. When interrupt condition occurs, an interrupt status flag is set to indicate the condition.

xirq

irq

BUSCTRLBus Controller - manages data exchange between CPU and several Internal and External Memories

COPCOP Watchdog Timer

PULSEACCAThis system is based on an 8-bit counter and can be configured to operate as a simple event counter or as a tool for gated time accumulation. Unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). Control bits allow the user to configure and control the pulse accumulator subsystem. Two maskable interrupts are associated with the system, each having its own controls and interrupt vector. The PAI pin associated with the pulse accumulator, can be configured to act as a clock (event counting mode) or as a gate signal, to enable a free-running of E divided by 64 clock, to the 8-bit counter (gated time accumulation mode). The alternate functions of the PAI (Pulse Accumulator Input) pin, present some interesting application possibilities.

SCIThe SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore, the differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and major logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. The logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, which can be used in applications with a modem.

SPIIt is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of Serial Clock Signal (SCK). It enables the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor communications, in a multi-master system. The Serial Clock Line (SCK) synchronizes shifting and sampling of the information, on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data rates are as high, as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector, automatically disables SPI output drivers, if more than one SPI devices simultaneously attempt to become a bus master.

TIMERMain Timer system, including Compare, Capture and Real Time Interrupt logic. This timer system is based on a free-running, 16-bit counter, with a 4-stage programmable prescaler. A timer overflow function allows software, to extend the timing capability of the system, beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time, when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals, or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in more detail.
A programmable periodic interrupt circuit (RTI) is tapped off the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer, in which the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain.
The timer subsystem involves more registers and control bits, than any other subsystem on the MCU. Each of the three input-capture functions, has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions, has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit the software, to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications, although it is not as efficient as a dedicated hardware, for some specific timing applications.

ALUArithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG) and related logic, such as arithmetic unit, logic unit, multiplier and divider.

Opcode DecoderPerforms an opcode decoding instruction and control functions for all other blocks.

DoCD^TM DoCD^TM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD^TM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCD^TM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCD^TM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).

docddatai

docddatao

docdclk

clkdocd

CHIPSELChip select's task is to minimize the amount of external glue logic, needed to interface the D68HC11F1 to external devices. The D68HC11F1 has four software configured chip selects, that can be enabled in expanded modes. The chip selects for I/O (CSIO1 and CSIO2) are used for I/O expansion. The program chip select (CSPROG) is used with an external memory, which contains the program code and reset vectors. The general-purpose chip select (CSGEN), is the most flexible and it is used to enable external devices.

IOPortsGeneral Purpose I/O Ports Shared with: Address and Data buses and peripheral functions.

porta

portb (7:0)

portc

portd

porte (7:0)

portf (7:0)

portg

ADC ControllerThe ADCCTRL used in D68HC11, provides communication between the internal ADC related registers and program running on D68HC11 and external ADC converter. Supports several Parallel and serial ADC.

adcdatai

adcdatao

adcclock

adccs

EEPROMCTRLExternal Serial EEPROM controller. This optional module, manages data exchange between D68HC11 and external EEPROM. During initialization, it copies contents of the whole external EEPROM, to internal EEPRAM (EEPROM Mirror implemented in standard parallel RAM). This module has several different options, therefore its details have been described in a separate document.

esi

eso

esck

ecs

clk

rst

cmf

Data bus Internal 8-bit data bus.

SFR data bus 8-bit Special Function Registers bus is used to inter-communication of all processors" peripherals. It allows easy management of system architecture.

Units

CTRLUNIT

Performs the core synchronization and data flow control. This module manages execution of all instructions.

Interrupt Controller

D68HC11 has implemented 17-level interrupt priority control. External interrupt pins are activated at low level (XIRQ, IRQ pins) or falling edge (IRQ pin). External interrupt requests by IRQ and XIRQ, are sampled each 1 system clock at the rising edge of CLK. The D68HC11 peripheral systems generate maskable interrupts, which are recognized only, if the global interrupt mask bit (I) in the CCR, is cleared. Maskable interrupts are prioritized according to default arrangement (look at the table below), established during reset. However, any source may be elevated to the highest maskable priority position, by using HPRIO register. When interrupt condition occurs, an interrupt status flag is set to indicate the condition.

BUSCTRL

Bus Controller - manages data exchange between CPU and several Internal and External Memories

COP

COP Watchdog Timer

PULSEACCA

This system is based on an 8-bit counter and can be configured to operate as a simple event counter or as a tool for gated time accumulation. Unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). Control bits allow the user to configure and control the pulse accumulator subsystem. Two maskable interrupts are associated with the system, each having its own controls and interrupt vector. The PAI pin associated with the pulse accumulator, can be configured to act as a clock (event counting mode) or as a gate signal, to enable a free-running of E divided by 64 clock, to the 8-bit counter (gated time accumulation mode). The alternate functions of the PAI (Pulse Accumulator Input) pin, present some interesting application possibilities.

SCI

The SCI is a full-duplex UART type asynchronous system, using standard, non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore, the differences in baud rate, between the sending device and the SCI, are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time and major logic decides the sense for the bit. For the start and stop bits, seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup), to ignore messages intended for a different receiver. The logic automatically wakes up the receiver, in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual Transmit Data Register Empty (TDRE) status flag, this SCI also provides a Transmit Complete (TC) indication, which can be used in applications with a modem.

SPI

It is a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of Serial Clock Signal (SCK). It enables the microcontroller, to communicate with serial peripheral devices. It is also capable of interprocessor communications, in a multi-master system. The Serial Clock Line (SCK) synchronizes shifting and sampling of the information, on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough, to interface directly with numerous standard product peripherals, from several manufacturers. Data rates are as high, as CLK/8. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols, to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included, to support interprocessor communications. A write-collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector, automatically disables SPI output drivers, if more than one SPI devices simultaneously attempt to become a bus master.

TIMER

Main Timer system, including Compare, Capture and Real Time Interrupt logic. This timer system is based on a free-running, 16-bit counter, with a 4-stage programmable prescaler. A timer overflow function allows software, to extend the timing capability of the system, beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time, when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals, or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in more detail.
A programmable periodic interrupt circuit (RTI) is tapped off the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer, in which the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain.
The timer subsystem involves more registers and control bits, than any other subsystem on the MCU. Each of the three input-capture functions, has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions, has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit the software, to control the edge(s), that trigger each input-capture function and the automatic actions, that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications, although it is not as efficient as a dedicated hardware, for some specific timing applications.

ALU

Arithmetic Logic Unit - performs the arithmetic and logic operations, during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG) and related logic, such as arithmetic unit, logic unit, multiplier and divider.

Opcode Decoder

Performs an opcode decoding instruction and control functions for all other blocks.

DoCD^TM

DoCD^TM Debug Unit is a real-time hardware debugger, which provides debugging capability of a whole SoC system. Unlike other on-chip debuggers, DoCD^TM ensures non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories, all SFRs, including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed, if any write/read occurs at particular address, with certain data pattern or without pattern. The DoCD^TM system includes three-wire interface and complete set of tools, to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off, to save silicon and reduce power consumption. When debugger is not used, it is automatically switched to power save mode. Finally, when debug option is no longer used, whole debugger is turned off.
The separate DoCD^TM clock line, allows debugger to operate in the SLEEP mode (major clock line CLK is stopped).

CHIPSEL

Chip select's task is to minimize the amount of external glue logic, needed to interface the D68HC11F1 to external devices. The D68HC11F1 has four software configured chip selects, that can be enabled in expanded modes. The chip selects for I/O (CSIO1 and CSIO2) are used for I/O expansion. The program chip select (CSPROG) is used with an external memory, which contains the program code and reset vectors. The general-purpose chip select (CSGEN), is the most flexible and it is used to enable external devices.

IOPorts

General Purpose I/O Ports Shared with: Address and Data buses and peripheral functions.

ADC Controller

The ADCCTRL used in D68HC11, provides communication between the internal ADC related registers and program running on D68HC11 and external ADC converter. Supports several Parallel and serial ADC.

EEPROMCTRL

External Serial EEPROM controller. This optional module, manages data exchange between D68HC11 and external EEPROM. During initialization, it copies contents of the whole external EEPROM, to internal EEPRAM (EEPROM Mirror implemented in standard parallel RAM). This module has several different options, therefore its details have been described in a separate document.