Digital Core Design

The Power of Intellectual Property

PIC DoCD - DCD on Chip Debugger

Power of Innovation is our primary target. That's why our R&D focuses on every IP Core detail. As a result of that anxiety there have been some unique solutions born. On of them is the PIC on-Chip Debugger (DoCDTM), which is complete debugging system, dedicated for DCD's DFPIC16XXX/DRPIC16XXX Microcontroller Cores. System consist of three major blocks:

The PIC DoCDTM provides a real-time and non-intrusive debug capability enabling a pre-silicon validation and post-silicon, on chip software debugging.
It allows hardware breakpoints, trace, variables watch, multi C sources debugging. The PIC DoCDTM Debug Software can work as a hardware debugger, as well as a software simulator - some tasks can be validated at software simulation level and after this step, you can continue real-time debugging, by uploading code into silicon.

As a PIC DoCDTM user, you can choose your favorite C compilers or assemblers for software development - it supports most of High Level Object files, produced by C/ASM compiler tools.

Go beyond the limits

System-on-Chip designs are facing the problem of inaccessibility of important control and bus signals, because they often lay behind the physical pins of the device - that makes traditional measurement instrumentation useless. The best way to get around those limitations, is to use on-chip debugging tools for the tasks verification and software debugging. Other advantage of an on-chip debugger, is improved design productivity in integrated environment, with graphical user interface. Ability to display/modify memories' content, processor's and peripherals' register windows, along with information tracing and ability to see the related C/ASM source code, are the key elements, that help to improve the design process and thereby, to increase productivity

Perfect service for free

The reason for the developement of the DoCDTM, was to provide our customers with the ability of easy system verification and software debugging, at no additional charges. Therefore, we have decided to add the complete debug system to each PIC IP Core - for free.

Now DCD's customers have the exceptional possibility, to obtain the complete solution for making their own PIC based SoC, with the ability to pre-silicon validation and post-silicon software debugging - at one place. It's a really unusual opportunity for the designer, to havethe ability to get a high quality IP Core and good on-chip debugging tool, from the same supplier.

Debug IP Core

The Debug IP Core block provides an in-circuit emulator feature. The Debug IP Core can be provided as VHDL or Verilog source code, as well as CPLD/FPGA EDIF netlist - depending on the customer requirements. Because many SoC designs have both power and area limitations, DoCDTM provides a scaled solution. Debug IP Core can be scaled to control gate count. The benefit is fewer gates - for lower use of power and core size, while maintaining excellent debug  abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation),  with less features availed in the final silicon.

  • Processor execution control
    • Run, Halt
    • Reset
    • Step into instruction
    • Skip instruction
    • Step over following subroutine
    • Step out curent subroutine
  • Read-write all processor contents
    • Program Counter (PC)
    • Program Memory
    • Data Memory
    • Special Function Registers (SFRs)
    • W Register
    • Hardware Stack
    • Stack Pointer
  • Unlimited number of software breakpoints
    • Program Memory
    • Data Memory
    • Special Function Registers (SFRs)
  • Hardware execution breakpoints
    • Program Memory
    • Data Memory
    • Special Function Registers (SFRs)
  • Hardware breakpoints activated at a
    • certain program address (PC)
    • certain address by any write into memory
    • certain address by any read from memory
    • certain address by write into memory a required data
    • certain address by read from memory a required data
  • Auto refresh of all opened Windows
  • Three-wire communication interface
  • Fully static synchronous design with no internal tri-states

Debug software

The DoCDTM Software (DS), is a Windows based application. It is fully compatible with nearly all existing PIC C compilers and Assemblers. The DS was designed to work in two major modes: software simulator mode and hardware emulator mode. Those two modes, allow the pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon - using emulator mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or ASM-level instructions or stopped at any of the breakpoints.

The DoCDTM Debug Software supports all DCD's PIC Cores (DRPIC16XXX, DFPIC16XXX) in the following architectures and particular configurations:

High Performance pipelined architecture - x4

Fast architecture - x2

Summarized PIC DoCD Features and options.

  • Two working modes
    • hardware emulator
    • software simulator
  • Source Level Debugging:
    • C level hardware/software breakpoints
    • C line execution
      • line by line
      • over function
      • out of function
      • skip line
    • ASM code execution
      • instruction by instruction
      • over instruction
      • out of function
      • skip instruction
    • ASM source code view
    • C source code view
  • Symbol explorer with hierarchical view of symbols:
    • modules
    • functions
    • blocks
    • variables
  • Symbolic debug including
    • variables
    • variable type
  • Contents sensitive Watch window
  • Unlimited number of software breakpoints
    • Program Memory
    • Data Memory (DM)
    • Special Function Registers (SFR)
  • Real-time hardware breakpoints
    • Program Memory
    • Data Memory (DM)
    • Special Function Registers (SFR)
  • Set/clear breakpoints in Source Code window
  • 1024 steps deep Software Trace
  • Dedicated windows for peripherals
  • Configurable auto refresh
  • Auto refresh of all windows during execution of program
    • Registers panel including W, OPTION, INTCON, PCL etc.
    • Data Memory (DM)
    • Special Function Registers (SFR)
    • Timer/Counter
    • I/O Ports
    • Hardware Stack
  • Load Program Memory content from:
    • Intel HEX files
    • OMF object files
    • COD object files
  • The system runs on a Windows 2000/2003/XP/7/8/8.1 (both 32 and 64 bits) PC


Hardware assisted debuger

A high-performance Hardware Assisted Debugger is connected to the target system containing the DCD's core, either in FPGA or ASIC. HAD2 is a small hardware adapter, that manages communication between the Debug IP Core inside silicon and a USB port of the host PC, running DoCDTM Debug Software.

System features description

SOFTWARE BREAKPOINTS:

An unlimited number of software breakpoints can be set anywhere in the physical address space of the processor (in Program Memory space, RAM and SFRs). If at least one software breakpoint is set, program is executed in automatic step by step mode, with checking, if certain breakpoint condition is met. Program execution is halted, when breakpoint condition is already met, and its execution can be resumed at any time in any appropriate mode.

HARDWARE BREAKPOINTS:

The number of hardware breakpoints is limited to four in different address spaces. Like software breakpoints, hardware execution breakpoints can be set in Program Memory space, RAM and SFRs. Like their software counter-parts, they stop program execution just prior an instruction is being executed. The difference is in the method of program execution. In this case program is run with full clock speed (in real-time) and processor is halted, when hardware signalizes real breakpoint condition.

MIXED MODE BREAKPOINTS:

Mixed breakpoint mode is also allowed and it means, that software and hardware breakpoints are mixed in the system. This gives you the flexibility in the debugging - for example, two different break conditions can be set at the same address space, by using software and hardware breakpoints. In each breakpoint mode, halt means: CPU is halted and instructions are no longer being fetched, all peripherals are running and are not affected by halt.


SCALED SOLUTION:

Due to the fact, that many SoC designs have both power and gate limitations, DCD provides a scaled solution. Debug extensions can be scaled to control gate counts. The benefits are fewer gates, lower power and core size while trading off debug capability.

HOST REQUIREMENTS:

A Pentium class computer with minimum 512 MB of memory, 32 MB of free space on Hard Disk, CD-ROM drive, USB port and Windows 2000/2003/XP/7/8/8.1 (both 32 and 64 bit) operating system, are required.


Symbol

Pins Description

Pin Type Description
docddatai input  DoCDTM data input
docddatao output DoCDTM data output
docdclk output  DoCDTM clock line
prgdatao output  Program memory data output
prgwe output Program memory write enable

Area utilization

Device vendor Area
Altera 760 LC
Xilinx 380 slices
ASIC 2800 gates

The table above gives a survey about the Debug IP Core area, in the FPGA and ASIC devices.