CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL. It is called “CPU friendly” because it efficiently relieves it through configurable registers and… few additional innovations.

DCD’s CAN FD FULL IP Core is a versatile and adaptable solution for incorporating Controller Area Network (CAN) functionality into various systems. This IP module can be implemented independently, as a part of an ASIC, or FPGA. It adheres to the ISO11898-1:2015 standard, enabling seamless communication in accordance with popular industry protocols.

DCD’s CEO, Jacek Hanke, inquires about the rationale behind labeling it as “CPU friendly.” – This distinction can be attributed to its enhanced filtering capabilities, which effectively alleviate the strain on CPU resources. By swiftly directing crucial messages to the buffers, they are promptly received without delay. Conversely, less critical data, such as temperature instructions, are stored in a FIFO (First-In-First-Out) arrangement. Once the FIFO reaches its capacity, all the accumulated messages are then transmitted to the CPU.

This module provides support for both Classical CAN and CAN FD but to establish a physical connection to the CAN bus, external transceiver hardware is required. DCD’s solution utilizes a single or dual-ported Message RAM, which is located outside of the module itself. This storage medium is connected to the CAN FD Full through the Generic Master Interface, facilitating efficient message handling.

The Host CPU can easily connect to the CAN FULL IP Core module via the 32-bit Generic Interface, enabling seamless integration and streamlined data exchange. DCAN FD Full supports all popular wrappers available on the market like e.g.

  • AMBA – APB / AHB / AXI Lite Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus

The IP core is available in two versions – Basic and Safety-Enhanced.

The DCAN FD Full has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and be provided together with detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step by step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.

This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD-SEMI may optionally deliver higher ASIL level ready IP. For further information and the optional features please contact our support.

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About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at