CryptOne IP Core involves the use of RSA asymmetric encryption scheme to realize a cryptosystem with a one-time pad (OTP). DCD’s solution is a broadly defined crypto system solution based on an asymmetric RSA with a hidden value of a component of a public key susceptible to crypto analysis and implementing the OTP rules.
Nowadays security is the key. That’s why CryptOne OTP offers the advantages of symmetric crypto systems with one-time pad while retaining the advantages of asymmetric systems. Our crypto system will enable the realization of unconditional security while eliminating OTP distribution problems and providing an unambiguous identification of users. – It should be emphasized that the current requirements for cohesive solutions for the European Union and e-services-like systems, as well as for sensitive data industry such as e-health and e-banking, necessitate the use of unambiguous and unique to each user identifiers that correspond to OTP – says Jacek Hanke, DCD’s CEO.
More information coming soon…
Eager to know more? Drop us an e-mail.DI3CM-FIFO IP Core compliant with MIPI I3C v1
IP Core provider and System-on-Chip design house from Poland introduced the DI3CM-FIFO IP Core. It incorporates all features required by the latest MIPI I3C specification. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance.
Digital Core Design maintains backward compatibility, to enable a smooth transition from I2C to I3C and focus on simple implementation. – The DI3CM-FIFO offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems – explains Piotr Kandora, Vice President of Digital Core Design.
The I3C interface uses an I2C-like interface with data line (SDA) and clock line (SCL). The open drain SDA line allows for slaves to take control of the data bus and initiate interrupts. The push-pull SCL line is used by the master to clock the communication bus up to 12.5 MHz. The master can dynamically assign 7-bit addresses to all I3C devices while supporting the static addresses of legacy I2C devices. This ensures full compatibility between MIPI I3C and I2C. The Core represents a shift in power performance while providing greater than an order of magnitude improvement in speed over I2C. I3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved in each mode are 11.1, 20, 23.5 and 33.3 Mbps, respectively, protected by I3C’s basic error detection mechanisms.
The I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, high-speed and other critical features that are currently covered by I2C and SPI.
- conforms to MIPI I3C v1.0 specifications
- MIPI Manufacturer ID: 0x03B3
- Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- Legacy I2C messaging
- I2C-like Single Data Rate messaging (SDR)
- Master operation with FIFO:
- Master transmitter
- Master receiver
- Supports flexible transmission speed modes:
- FAST-PLUS (up to 1000 kb/s)
- SDR (up to 12,5 Mb/s)
- Configurable FIFO size up to 256 Bytes
- Configurable SDA/SCL glitch filter
- Software programmable SDA/SCL bus timings
- Multi-master systems supported
- Interrupt generation
- Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
- Configurable interface allows easy connection to standard bus interfaces: APB, AHB, 8051, 80251, others
- Support for in-band interrupts
- Support for I3C common command codes
- Dynamic address assignment (DAA) support
- Command queue support
- Low power management support
- Fully interoperable with third-party I3C master and slave solutions
- Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset
The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.
The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. DCD’s IP Core contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.
– It supports 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates – explains Tomek Krzyzak, VP of DCD – of course we know that some might ask why not USB 3.0? – but honestly speaking in 99.9% of embedded applications, USB 2.0 is more than enough.
The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
DCD’s USB IP Core portfolio includes also: Audio Platform USB 2.0 – Audio Devices Design Platform, USB 2.0 HID Platform – USB 2.0 Human Interface Devices Design Platform, USB 2.0 MS Platform – USB 2.0 Mass Storage Devices Design Platform, USB 2.0 DUSB2 – USB 2.0 Device Controller USB 2.0 (UTMI interface).
- Full compliance with the USB 2.0 specification
- Full-speed 12 Mbps operation
- High-speed 480 Mbps operation
- Software configurable EP0 control endpoint size 8-64 bytes
- Software configurable 15 IN/OUT endpoints:
- configurable number of endpoints
- configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
- configurable direction of each endpoint
- configurable size of each endpoint: 8-1024 bytes
- Supports ULPI Transceiver Macrocell Interface
- Synchronous RAM interface for FIFOs
- Suspend and resume power management functions
- Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
- Allows operation from a wide range of CPU clock frequencies
- Fully synthesizable
- Static synchronous design
- Positive edge clocking
- No internal tri-states
- Scan test ready
The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz. The minimal usable D32PRO CPU starts from 10.6k/6.8k gates when optimized for area. Dynamic power is 7 microwatts/MHz with a 90 nm process (DCD’s IP Cores are synthesizable and foundry independent). The D32PRO has been equipped with C compiler and integrated CPU configurator. This makes DCD’s CPU fully configurable, both for ultra-low energy and for power-user projects.
The D32PRO is a deeply embedded, royalty-free 32-bit CPU. Drawing on its valuable experience – like the world’s fastest 8051 – Digital Core Design created completely new, RISC 32-bit CPU. This silicon proven CPU enables engineers to tailor it to their needs – The D32PRO is fully scalable, hence it can be easily adjusted to get the efficiency comparable to ARM Cortex M0-M3 – explains Tomek Krzyzak, DCD’s vice-president – but there’s no problem to run the Core with maximal performance to get up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz.
The D32PRO has been designed from scratch by DCD’s engineers. Since 1999 the company has released over 70 different architectures, among them is the DQ80251, world’s fastest 8051 CPU. – Of course, the D32PRO is an effect of our market experience – adds Krzyzak – but it’s a completely new, innovative solution. We are engineers, so we know the problems we all face in our work – why waste silicon, why limit performance, why shorten peripherals list? The D32PRO answers all these questions.
All peripherals on board
The D32PRO has been equipped with Floating Point Coprocessor and great variety of available peripherals like e.g. USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC, Smart Card etc. Other peripherals can be effortlessly added to the CPU by using standardized interfaces.
Variable pipeline – ultimate code density
The D32PRO is a universal & fully configurable solution, which effectively executes application codes with many jumps (e.g. switching decision tree) as well as homogeneous ones (e.g. arithmetic operations). This wouldn’t be possible without variable pipelining. Another innovation is brought in the command list, which is based on special instructions – derivatives to the higher level language like e.g. C. That approach enabled ultimate code density, which goes in hand with efficient and compact instructions set. Variable length instructions are based on 16 bits and can be executed conditionally. The D32PRO implements the best features of the embedded microcontrollers, where one of them enables efficient cooperation with the at-tached peripherals, thanks to dedicated bit instructions.
The D32PRO has been equipped with 13 general registers R0-R12 and most of them are being refreshed automatically after interruption. Thanks to it the CPU accelerates interrupts and context switching in real time systems. And if it’s still not enough, the D32PRO has been equipped with one non-maskable and dozens of real-time reconfigurable interrupts: like its activity, priority level and number of automatically stacked registers.
Low energy for (not only) IoT
The D32PRO emphasizes low energy consumption, which is crucial in modern electronics. This is achieved thanks to special PMU (Power Management Unit), which dynamically controls the clock’s frequency. Thanks to it an engineer can program energy-saving mode for the CPU, where all the peripherals will be working with nominal clock. Moreover, the CPU itself can be moved to STOP mode with the clock detached from it. Then it can return to normal mode by an interrupt from any peripheral. In order to save additional power, the CPU can easily switch off the peripherals which are unused at the current moment.
Debugger – Bootloader
The D32PRO, similarly to DCD’s 8051 IP Cores, is delivered with a built-in hardware debugger. But this special solution has been tailored for 32-bit CPU, that’s why it enables full control from Eclipse level (complete Eclipse debugging system with GCC => USB 2.0 cable => D32PRO). Moreover, in DCD’s debugger only two pins have been used as optimal tradeoff between communication throughput and consumed resources, when in competitive solutions communication needs at least 5 pins (JTAG). Hardware bootloader unit enables firmware memory updates directly from external low cost Flash memory connected through the (Q)SPI interface. Moreover, the bootloader is equipped with hardware encryption mechanism which significantly protects firmware against reverse engineering.
More information: www.dcd.pl
- D32PRO, deeply embedded, royalties-free 32bit CPU
- CoreMarks/MHz CoreMarks: 2.41
- Dhrystone 1.48 / 2.67 DMIPS/MHz
- Power consumption (90nm) under 7µW/MHz (90LP)
- Size (90nm) 10.6k/6.8k gates
DCAN FD, a Configurable CAN Bus Controller with Flexible Data-Rate targets autonomous cars & ADAS systems
Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has introduced the newest IP Core. The DCAN FD IP Core is a configurable CAN Bus controller with Flexible Data-Rate. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) in accordance to ISO 11898-1:2015. The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbps (even up to 8Mbps) and the payload (data field) is up to 64 byte long. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized.
Poland, Bytom, September the 26th, 2016. The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) – in accordance to ISO 11898-1:2015.
Standard CAN requirements become insufficient in modern automotive. The carmakers demand more bandwidth and more throughputs for most CAN-based in-vehicle networks. The DCAN FD IP Core is also a good alternative for non-automotive projects where not the increasing speed is the target. The longer payload (more than 8 byte) becomes crucial then.
The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbps (even up to 8 Mbps) and the payload (data field) is up to 64 byte long. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes need to be re-synchronized. – The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing scheme – explains Tomasz Krzyzak, VCEO in Digital Core Design. Hardware message filtering and 128 byte receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN FD is described at RTL level, allowing target use in FPGA or ASIC technologies.
- Designed in accordance to ISO 11898-1:2015
- Supports CAN 2.0B and CAN FD frames
- Support up to 64 bytes data frames
- Flexible data-rates supported
- 8/16/32-bit CPU slave interface with small or big endianness
- Simple interface allows easy connection to CPU
- Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
- Data rate up to 8 Mbps
- Hardware message filtering (dual/single filter)
- 128 byte receive FIFO and transmit buffer
- Overload frame is generated on FIFO overflow
- Normal & Listen Only Mode
- Transceiver Delay Compensation up to three data bit long
- Single Shot transmission
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Fully synthesizable
- Static synchronous design with positive edge clocking and synchronous reset
- No internal tri-states
- Scan test ready
- Available system interface wrappers:
- AMBA – APB Bus
- Altera Avalon Bus
- Xilinx OPB Bus
- Source code:
- VHDL Source Code or/and
- VERILOG Source Code or/and
- FPGA Netlist
- VHDL /VERILOG test bench environment
- Active-HDL automatic simulation macros
- NCSim automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Technical documentation
- Installation notes
- HDL core specification
- Synthesis scripts
- Example application
- Technical support
- IP Core implementation support
- 3 months maintenance
- Delivery of the IP Core and documentation up dates, minor and major versions changes
- Phone & email support.
Information about Digital Core Design:
The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 75 times faster than the standard solution. The same, D32PRO, which is a royalty-free and fully scalable 32-bit CPU creates new possibilities for modern projects. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 500 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.