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DFSPI IP Core from DCD supports all serial memories available on the market.

CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL. It is called “CPU friendly” because it efficiently relieves it through configurable registers and… few additional innovations.

DCD’s CAN FD FULL IP Core is a versatile and adaptable solution for incorporating Controller Area Network (CAN) functionality into various systems. This IP module can be implemented independently, as a part of an ASIC, or FPGA. It adheres to the ISO11898-1:2015 standard, enabling seamless communication in accordance with popular industry protocols.

DCD’s CEO, Jacek Hanke, inquires about the rationale behind labeling it as “CPU friendly.” – This distinction can be attributed to its enhanced filtering capabilities, which effectively alleviate the strain on CPU resources. By swiftly directing crucial messages to the buffers, they are promptly received without delay. Conversely, less critical data, such as temperature instructions, are stored in a FIFO (First-In-First-Out) arrangement. Once the FIFO reaches its capacity, all the accumulated messages are then transmitted to the CPU.

This module provides support for both Classical CAN and CAN FD but to establish a physical connection to the CAN bus, external transceiver hardware is required. DCD’s solution utilizes a single or dual-ported Message RAM, which is located outside of the module itself. This storage medium is connected to the CAN FD Full through the Generic Master Interface, facilitating efficient message handling.

The Host CPU can easily connect to the CAN FULL IP Core module via the 32-bit Generic Interface, enabling seamless integration and streamlined data exchange. DCAN FD Full supports all popular wrappers available on the market like e.g.

The IP core is available in two versions – Basic and Safety-Enhanced.

The DCAN FD Full has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and be provided together with detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step by step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.

This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD-SEMI may optionally deliver higher ASIL level ready IP. For further information and the optional features please contact our support.

More information: https://www.dcd.pl/product/can-fd-full/

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

DFSPI IP Core from DCD supports all serial memories available on the market.
Digital Core Design, the leading IP Core provider and System-on-Chip design house presents its latest DFSPI IP Core for access to NOR and NAND Flash Devices. And if universal NOR & NAND Flash IP is not enough… DCD’s DFSPI IP Core also supports MRAM, pSRAM, DRAM, and EEPROM – combining ease of use with reliability, low power, and speed under all conditions, including automotive, industrial, and other applications.

DFSPI IP Core is a real “combo” between all SPI IP Cores available on the market – it’s an SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL, QUAD, OCTAL SPI Bus Controller with DDR / DTR support and optional AES Encryption) + NOR & NAND Flash Memory Support for all serial memories available on the market.

– As an option, the DFSPI controller has built-in support for HyperBusTM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification – explains Jacek Hanke, DCD CEO The same the SPI Controller allows easy communication with all available SPI FLASH memories.

The DFSP IP Core is compatible with the xSPI JESD251 standard, which can be accessed through a standard AXI4 slave interface. It offers backward compatibility with Octal SPI, QSPI, DSPI, and SPI interfaces. Furthermore, it supports the JEDEC SFDP Standard. The IP allows users to quickly access memory from the xSPI device in SPI mode. Alternatively, users can issue a command to switch to a different mode. Additionally, a DMA command can be used to copy memory from the xSPI device to any other location on the bus.

The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface with higher-performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, delivering it in the exact configuration that meets users’ requirements.

DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. These cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

More information: https://www.dcd.pl/product/dfspi/

 

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

One solution for complex CAN architectures

DCD provides the DCAN FD IP core for the implementation of standalone CAN (FD) controllers. The company’s CAN-All ecosystem considers automotive safety standards and expands towards CAN XL.

 

More detailed information can be found in CAN in Automation Newsletter and webpage: https://can-newsletter.org/uploads/media/raw/9b65ce48915450ad8463848124762907.pdf

Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller

The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. – It is a technology-independent design that can be implemented in a variety of process technologies – explains Jacek Hanke, DCD-SEMI CEO.

The DESPI is flexible enough to interface directly with numerous peripherals. The system may be configured either as master or as slave, and depending on the core configuration, the _in or _out lines will be utilized. Its serial clock can run up to 66MHz – adds Hanke.

The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration with the target design requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs, capable of storing up to 4096+16 bytes (Header and maximal data payload) in separate buffers for every eSPI channel. (Peripheral Channel Posted and Non-Posted, Virtual Wire Channel, Out of Band Channel, Flash Access Channel).

Additionally, customizable Peripheral Channel Memory and IO port, Virtual Wire lines and event lines are also supported. An interesting and unique feature is the Alert mechanism, used by the eSPI Slave to request service from the eSPI master.

The controller is capable to operate in several eSPI configurations:

The DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. The DCD SPI cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

More information: https://www.dcd-semi.com/product/despi/

DCD adds extra features to LIN IP Core and GuardKnox license the solution

DCD, a leading IP Core provider and SoC design house from Poland, mastered the unique LIN IP Core with UART half-duplex enhanced functionality. The newest Core conforms to ISO17987-6:2016 protocol conformance test specification for Functional Safety. GuardKnox, an Israeli-based company with subsidiary locations in Munich, Germany, and Detroit, Michigan –integrated DCD’s LIN IP Core as part of their CommEngine product– a holistic solution for communication routing and switching capabilities.

DCD’s LIN IP Core’s been developed as ISO26262 Safety Element out of Context (SEooC). – It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation – says Jacek Hanke, DCD’s CEO – we also added another handy feature to this LIN IP Core – UART half-duplex enhanced functionality.

The IP core is available in two versions – Basic and Safety-Enhanced. The second has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instructions to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.

SPI: These Three Letters Denote Everything You Asked For

Electronics are everywhere. Many times, as frequent users, we do not even notice a “paradigm change” in the things we use on regular basis. We use a fridge, but we do not care that there is a microcontroller (MCU) and a set of sensors instead of a basic thermostat. We use a tablet with a touchscreen, but we do not care how the screen-tap information is transmitted to the MCU. We use SD cards to store photos and movies in our smartphones, cameras, and other portable devices, but the card’s interface is a big mystery for many — at least for those who have never dug into the details.

Every electronic device must be equipped with an MCU — also called the device’s brain. An MCU is a tiny computer fabricated on a single chip. It contains at least one central processing unit (CPU), memory, and input/output peripherals. When we talk about peripherals, the serial peripheral interface (SPI) becomes crucial. SPI plays an essential role enabling fast, reliable, and simple short-distance communication. It is also simple enough to implement and has a low resource usage. This is reflected in the statistics: EE Times Asia shows the most popular MCUs, and each and every one of them is equipped with SPI controller; the same in Electronics-Lab.com’s ranking and other rankings. So it’s obvious that SPI is a must for every MCU.

This article focuses on the most important details of the modern SPI interfaces, which are improved by many useful features. But to start, let us discover the history of the modern SPI interface, because even the old, most basic SPI interfaces are still in use.

Brief history

SPI was developed by Motorola in the 1980s. It is a synchronous serial communication interface used in embedded systems. The single SPI specification (the first specification) describes the master-slave architecture (full-duplex), typically with one master device and multiple slave devices. It is also called the four-wire serial bus:

Why did SPI become so popular? Mainly because of its simplicity. There are no start nor stop bits, there is no parity like in UART bus, and it enables higher transfer rates than I2C. There are plenty of pros.

The logic resources needed to implement SPI are very few: Single SPI simultaneous transmission and reception synchronized by serial clock can be modeled as two shift registers in a loop, as it has been presented below.

Figure 1: SPI concept model

Figure 1: SPI concept model

In reality, the SPI controller internal architecture is much more complicated than it has been shown in Figure 1, featuring more control registers, port control logic, and interrupt control. The example architecture can be found in Motorola’s SPI standard, “SPI Block Guide.”

The clock phase and polarity are configurable. There are four transfer formats available:

SPI: These Three Letters Denote Everything You Asked For

CPOL defines whether SCK is low (0) or high (1) when bus is idle (nSS is high).

CPHA defines whether the first (0) or second (1) SCK edge after nSS has been asserted (nSS is low) is used to sample data.

If data is sampled at the rising SCK edge, then shift occurs at the falling SCK edge.

If data is sampled at the falling SCK edge, then shift occurs at the rising SCK edge.

Figure 2: CPHA = 0

Figure 2: CPHA = 0

Figure 3: CPHA = 1

Figure 3: CPHA = 1

The shift registers are both 8 bits (in master and in slave). Data is shifted out with the most significant bit first and shifted in with the least significant bit first. The transmission is full-duplex because both the master and slave send and receive data simultaneously.

MISO and MOSI lines can be combined into one bidirectional line, but the transmission will be reduced to half-duplex. In this case, only three wires are needed for SPI transmission/reception.

There are many implementations of SPI bus controllers available on the market. Just as an example, DCD-SEMI’s DSPI is a fully configurable SPI master/slave device. It is flexible enough to interface directly with numerous standard peripherals like memories, sensors, etc. The IP is easy to use and utilizes a low amount of logic resources — just as the SPI should be.

Multi-line SPI

SPI is frequently used in communication with serial memories. The memory size can be large, which enforces the need of faster transfers. SCK cannot increase infinitely, so the first thought is to increase the number of data lines, not to unnecessarily increase the number of wires. it is better to stay with the half-duplex transmission.

As the first, dual SPI has been introduced. MOSI has become SIO0 (Serial I/O 0) and MISO has become SIO1. SIO0 carries even bits and SIO1 carries odd bits. The bus throughput becomes doubled.

Then the quad SPI has been mastered. New data lines have been added: SIO2 and SIO3. The bit transmission scheme looks as follows:

Figure 4: Dual and quad SPI bit sequence

Figure 4: Dual and quad SPI bit sequence

The bus throughput becomes doubled again, and each data byte can be sent in only two SCK cycles.

The SPI transfer from/to serial memory consists of several phases: Instruction (command), Address, Data, and, optionally, Checksum. Some commands are required to be sent in single SPI mode, while Address and Data are sent in multi-IO mode.

Further extending quad SPI, some devices increase the transfer rate by using double-data–rate (DDR) transmission, wherein data lines are sampled both on the rising and falling edge simultaneously, so every data byte is sent in just one SCK cycle. An example is shown in Figure 5.

Figure 5: DDR quad SPI transfer

Figure 5: DDR quad SPI transfer

One could ask: If we are already using four data lines, why not expand further? So thought the engineers who introduced octal SPI. In single-data–rate (SDR) mode, 1 byte is sent in one SCK cycle, and in DDR mode, 2 bytes are sent in one SCK cycle. The bandwidth increases significantly. An example is shown in Figure 6.

Figure 6: Octal SPI DDR transfer

Figure 6: Octal SPI DDR transfer

The transfer format shown in Figure 6 has its limitations. Instruction is sent repeated, as 2 bytes, to preserve an even number of bytes in transfer, because sampling is done on every SCK edge. Alternatively, the command can be sent in SDR mode. Address and Data phases must also contain an even number of bytes.

By now, the CPOL and CPHA settings have lost their meaning. Octal SPI DDR transfers are conducted only in SPI mode 0.

For HDL designers, it’s common to develop backward-compatible SPI master/slave controllers. DCD-SEMI finds customer’s interest in the DQSPI that supports single, dual, and quad SPI transfers, while DOSPI supports single, dual, quad, and octal SPI transfers. Both support DDR transfers, support multiple SPI slaves, implement a dedicated FIFO memory, and are available with the most common CPU bus interfaces. In single SPI mode, all of Motorola’s SPI configurations are supported.

eXecute In Place

Thanks to DDR and quad/octal transfers combined with high SCK frequency, it became possible to execute programs directly from a serial memory instead of copying the program memory into RAM. The program code must be stored in nonvolatile memory and the serial flash memory is cheaper than a parallel. The SPI controller in eXecutive In Place (XIP) mode is considered a bus bridge: From the “CPU’s point of view,” it is a simple memory that can be accessed parallel, and from the “SPI memory’s point of view,” it is just an ordinary SPI master. The CPU read transfers are performed with zero latency, if the program is executed linear (address after address) or the jump does not cross boundary of memory page, stored in controller’s FIFO memory. Also, in a typical embedded system, the MCU does run on significantly lower frequency than the SPI controller, so the data is available immediately, even if the next memory page has to be read.

Figure 7: XIP mode block diagram

Figure 7: XIP mode block diagram

In XIP mode, there is also available the regular register access to SPI controller. This mode is also used to configure the IP’s internal registers.

Typically, XIP is used in First Stage Boot Loader, e.g., in embedded systems, Linux OS, BIOS, etc. The SPI controller is preconfigured on power-on reset, and after the reset is deactivated, it starts reading the first memory page. There are also attempts to prepare file systems based on XIP.

The aforementioned DQSPI/DOSPI, as well as the latest SPI flash controller (DFSPI) are also available with the XIP interface. This ensures optimal system performance and wide configuration options.

Recently, another interesting feature can be found in SPI controllers, like in the DFSPI. For best performance and lowest software overhead, the automatic configuration feature can be used. The SPI controller is equipped with additional small memory, which acts as the lookup table, storing predefined device configuration. The memory content is prepared before the synthesis and implementation, or in a more advanced solution, it can be modified like an ordinary internal register. After writing Instruction/Command into the SPI controller, the device is automatically configured. The configuration may cover:

eXpanded Serial Peripheral Interface

Based on the information from this article, we can see how handy SPI is. JEDEC created a new standard above SPI, with limited backward compatibility. The standard defines commands for general-purpose read and write of any device, which helps in system development. eXpanded Serial Peripheral Interface (xSPI) helps to develop device-provider–independent applications.

xSPI enables flexible configuration of SPI transfer mode (single, dual, quad, octal) and SDR/DDR mode. Instruction, Address, and Data can all be independently performed in one of the modes as follows:

For example, a 4S-4D-4D can be performed.

HyperBus became part of xSPI in 2017. It has been named xSPI type 8D-8D-8D Profile 2.0.

In both HyperBus and xSPI, high clock rates can be achieved by using a separate clock signal for transmission (master-generated) and for reception (slave-generated/returned with internal delay). This provides best timing reference and is source-dependent. The data and strobe must be synchronous, while the strobe and SCK have no phase dependency.

Figure 8: xSPI bus lines

Figure 8: xSPI bus lines

Figure 9: xSPI transfer

Figure 9: xSPI transfer

Figure 10: xSPI transfer

Figure 10: xSPI transfer

The DFSPI is one of the SPI controllers already supporting xSPI.

It’s worth mentioning that recently, a new Xccela Consortium has been established. The new standard is xSPI-compliant at the physical layer. It focuses on the plug-and-play compatibility between products and provides complete device specifications and guidelines for designers.

Serial bus replaces parallel bus

Enhanced Serial Peripheral Interface (eSPI) uses the same timing and electrical requirements as regular SPI, but it is designed to replace the deprecated LPC bus, which has replaced the ISA bus on the PC’s motherboard. The LPC messages and much more are replaced by in-band SPI transfers. eSPI is low-power, energy-efficient, and configurable bandwidth bus. Even though at the physical layer, the eSPI uses the same SPI bus, the protocol and requirements are different.

First of all, eSPI introduces a new signal “alert,” which works like an interrupt request from the slave to the master. If the master asks for data and the data cannot be immediately returned, the transmission is ended and the slave requests transmission completion after the data has been prepared. Alert can only be driven when bus is idle (CS is high).

Figure 11: eSPI bus lines

Figure 11: eSPI bus lines

Each eSPI transfer consists of a Command and Response phase divided by a Turnaround phase. In Command, the master drives information on the bus. In Turnaround, all I/O lines are tri-stated, and the bus mastering is given to the slave. In Response, the slave drives information on the bus. Both Command and Response are supervised by CRC. In Response, the eSPI slave also returns the internal slave status register state.

Figure 12: eSPI transfer

Figure 12: eSPI transfer

Without going deeper into the details of the eSPI bus, we can see how different it is — also a good example of the usage of the SPI bus. xSPI gathers all the previous SPI standards together, while eSPI is a totally different standard. eSPI has been created by Intel and is best tailored for motherboards with Intel CPU (Intel architecture Skylake U or newer).

eSPI standard goes back to 2016. As we can see in different vendors’ portfolios, it is not so common like xSPI, but DCD-SEMI has already got a dedicated DESPI controller available.

Summary

SPI has evolved over the last four decades — from a basic concept to an advanced serial bus. But one thing remains the same: It is commonly used and can be found everywhere. But before you use an SPI controller in your next project, it will be worthwhile to compare the available IPs and to choose the best-fitting one in your design. As an example, you can take a look at the table below. All SPI IP cores, but the functionality differs a lot.

SPI: These Three Letters Denote Everything You Asked For

SHA IP Core with native SHA2-256 HMAC support

Our latest DSHA2-256 IP Core is a universal solution which efficiently accelerates SHA2-256 hash with native HMAC mode. This IP targets authenticity and data integrity verification in digital signature protocols and all aspects of secured communication. It’s worth to mention that due to its unique features, the DSHA2-256 IP Core might also be used in crypto currency computations acceleration.

The DCD’s DSHA2-256 is a universal solution which accelerates SHA2-256 hash function compliant with FIPS PUB 180-4. It computes message digest either in 256 and 224 bit modes. Allowed input message length is up to 264 – 1 bit. The core is fully configurable, which significantly reduces design time. – Native support of the SHA2-256 HMAC (keyed-Hash Message Authentication Code) is a… key – says Jacek Hanke, DCD’s CEO – this cryptographic function defined in RFC 2104 is a must in all kinds of secured communication.

The DSHA2-256 is suitable for authenticity and data integrity verification in digital signature protocols and all other communication where security is the key. It might also be used in crypto currency computations accelerating. DCD’s IP Core offers context swapping feature which is extremely useful in complex systems with a task’s preemption mechanism and software managed or custom HMAC scheme.

SHA2 is a family of cryptography secure one-way compression functions based on Merkle-Damgard structure, the 256 version sequentially process 512 bit input blocks during 64 rounds. From arbitrary length input message (maximum 264 – 1 bits) it produces fixed 256 or 224 bit length digest in a way that it is practically infeasible to invert it (get original message from its digest). Such property is called a one-way function.  Cryptographic security of SHA2-256 is assumed at 128 bit level (112 bit in case of SHA2-224) which makes it appropriate to use in security applications. Some of them need to prove knowledge or possession of some secret data while computing message digest. For such authentication purpose the HMAC function has been designed. It combines both secret key and cryptography secure hash function (like SHA2-256).

Key features:

Applications

Deliverables

The list of deliverables consists of:

The Most Innovative IP Core of the Year 2019

CryptOne, DCD’s latest cryptographic IP Core, has been awarded with “2019 Most Innovative IP of the Year” by Design & Reuse during IP SoC Days in Shanghai, China. 

IP SoC Day has ben organised in September the 19th, 2019 by Design&Reuse in Shanghai, China. More than 25 well know IP Core & SoC companies decided to present their products during the show and several hundreds of other – to participate.

Here’s detailed program: http://www.design-reuse-embedded.com/ipsocdays/ipsocdays2019/china2019/#

Just 10 from these companies have been nominated for “The Most Innovative IP Core of the Year” Award. Among them Digital Core Design with our latest CryptOne IP Core. 100% safe cryptographic system got the biggest attention (and votes, thank you!) which denotes our WIN!

If you’re curious about the winner and the best runner-ups, here’s the link: http://www.design-reuse-embedded.com/ipsocdays/ipsocdays2019/china2019/files/bio/BestPrize.jsp#

DCD is celebrating 20th Anniversary

More than 500 000 000 electronic devices around the globe have been based on DCD’s IP Cores. Among them one can easily find YOUR solution. Taking the chance we’d like to thank you for our hitherto cooperation, cause this 20th anniversary for DCD wouldn’t be possible without you.

Taking the chance to thank you, we’ve prepared some gifts for you. First one is our summer promo – 20% off from the IP Core price for 20th anniversary. Sarting from June till September you can easily license any of our IP Core with great discount. No matter if it’s 32-bit royalty-free CPU, I3C or World’s Fastest 8051 IP Core – they’re all here, waiting for you and your project. Just drop us an e-mail and let us know what you need.

The second one is our… knowledge. That’s why, taking the chance, we’ll be publishing some of our best case studies from last 20 years. First one is here: http://mailchi.mp/77bf92df4dd1/cryptographic-ip-core-system

And last but not least – please remember, we’re here for you! Let us know by e-mail, social media, phone what can we do for you.

 

Meet us at Hannover Messe 2019

DCD unveils CryptOne cryptographic system

at Hannover Messe, Germany (01-05.04.2019) – the biggest industry fair in Europe!

 

Digital Core Design, celebrating 20th anniversary in 2019, mastered a completely new and innovative cryptographic systeme. Basing on two decades of IP Core market experience and best Polish cryptographers solutions, DCD’s programmers introduced:

CryptOne, a 100% safe cryptographic system.

What is the top concern for developing IoT solutions? 39% of the answers stated: security (Copyrighe 2018, Eclipse Foundation, Inc.). That’s why Digital Core Design decided to create an innovative cryptographic system which will boost encryption & decryption performance. Eager to know more? Join us in Hannover, Germany starting from April 1st till 5th. Official press conference will be held on Monday, 1st of April at Polish National Booth (Hall 27, H12) – 12:00 CET.

 

 

 

CryptOne – 100% safe crypto CPU IP Core

CryptOne IP Core involves the use of RSA asymmetric encryption scheme to realize a cryptosystem with a one-time pad (OTP). DCD’s solution is a broadly defined crypto system solution based on an asymmetric RSA with a hidden value of a component of a public key susceptible to crypto analysis and implementing the OTP rules.

Nowadays security is the key. That’s why CryptOne OTP offers the advantages of symmetric crypto systems with one-time pad while retaining the advantages of asymmetric systems. Our crypto system will enable the realization of unconditional security while eliminating OTP distribution problems and providing an unambiguous identification of users. – It should be emphasized that the current requirements for cohesive solutions for the European Union and e-services-like systems, as well as for sensitive data industry such as e-health and e-banking, necessitate the use of unambiguous and unique to each user identifiers that correspond to OTP – says Jacek Hanke, DCD’s CEO.

More information coming soon…

Eager to know more? Drop us an e-mail.

DI3CM-FIFO IP Core compliant with MIPI I3C v1

IP Core provider and System-on-Chip design house from Poland introduced the DI3CM-FIFO IP Core. It incorporates all features required by the latest MIPI I3C specification. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance.

Bytom, December the 5th, 2017. The I3C (Improved Inter Integrated Circuit) is the next generation of the I2C. Keeping the best assets from its elder brother, the I3C offers major improvements in terms of use, power consumption and performance. The Core uses just two pins and consumes a fraction of energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced to a controller or application processor.

Digital Core Design maintains backward compatibility, to enable a smooth transition from I2C to I3C and focus on simple implementation. – The DI3CM-FIFO offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems – explains Piotr Kandora, Vice President of Digital Core Design.
The I3C interface uses an I2C-like interface with data line (SDA) and clock line (SCL). The open drain SDA line allows for slaves to take control of the data bus and initiate interrupts. The push-pull SCL line is used by the master to clock the communication bus up to 12.5 MHz. The master can dynamically assign 7-bit addresses to all I3C devices while supporting the static addresses of legacy I2C devices. This ensures full compatibility between MIPI I3C and I2C. The Core represents a shift in power performance while providing greater than an order of magnitude improvement in speed over I2C. I3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved in each mode are 11.1, 20, 23.5 and 33.3 Mbps, respectively, protected by I3C’s basic error detection mechanisms.
The I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, high-speed and other critical features that are currently covered by I2C and SPI.

Key features:

DUSB2-ULPI, an USB 2.0 device controller with ULPI interface

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. DCD’s IP Core contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.
– It supports 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates – explains Tomek Krzyzak, VP of DCD – of course we know that some might ask why not USB 3.0? – but honestly speaking in 99.9% of embedded applications, USB 2.0 is more than enough.
The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
DCD’s USB IP Core portfolio includes also: Audio Platform USB 2.0 – Audio Devices Design Platform, USB 2.0 HID Platform – USB 2.0 Human Interface Devices Design Platform, USB 2.0 MS Platform – USB 2.0 Mass Storage Devices Design Platform, USB 2.0 DUSB2 – USB 2.0 Device Controller USB 2.0 (UTMI interface).

 

Technical information:
D32PRO, fully scalable and royalty-free 32-bit CPU

The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz. The minimal usable D32PRO CPU starts from 10.6k/6.8k gates when optimized for area. Dynamic power is 7 microwatts/MHz with a 90 nm process (DCD’s IP Cores are synthesizable and foundry independent). The D32PRO has been equipped with C compiler and integrated CPU configurator. This makes DCD’s CPU fully configurable, both for ultra-low energy and for power-user projects.

The D32PRO is a deeply embedded, royalty-free 32-bit CPU. Drawing on its valuable experience – like the world’s fastest 8051 – Digital Core Design created completely new, RISC 32-bit CPU. This silicon proven CPU enables engineers to tailor it to their needs – The D32PRO is fully scalable, hence it can be easily adjusted to get the efficiency comparable to ARM Cortex M0-M3 – explains Tomek Krzyzak, DCD’s vice-president – but there’s no problem to run the Core with maximal performance to get up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz.
The D32PRO has been designed from scratch by DCD’s engineers. Since 1999 the company has released over 70 different architectures, among them is the DQ80251, world’s fastest 8051 CPU. – Of course, the D32PRO is an effect of our market experience – adds Krzyzak – but it’s a completely new, innovative solution. We are engineers, so we know the problems we all face in our work – why waste silicon, why limit performance, why shorten peripherals list? The D32PRO answers all these questions.

All peripherals on board

The D32PRO has been equipped with Floating Point Coprocessor and great variety of available peripherals like e.g. USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC, Smart Card etc. Other peripherals can be effortlessly added to the CPU by using standardized interfaces.

Variable pipeline – ultimate code density

The D32PRO is a universal & fully configurable solution, which effectively executes application codes with many jumps (e.g. switching decision tree) as well as homogeneous ones (e.g. arithmetic operations). This wouldn’t be possible without variable pipelining. Another innovation is brought in the command list, which is based on special instructions – derivatives to the higher level language like e.g. C. That approach enabled ultimate code density, which goes in hand with efficient and compact instructions set. Variable length instructions are based on 16 bits and can be executed conditionally. The D32PRO implements the best features of the embedded microcontrollers, where one of them enables efficient cooperation with the at-tached peripherals, thanks to dedicated bit instructions.
The D32PRO has been equipped with 13 general registers R0-R12 and most of them are being refreshed automatically after interruption. Thanks to it the CPU accelerates interrupts and context switching in real time systems. And if it’s still not enough, the D32PRO has been equipped with one non-maskable and dozens of real-time reconfigurable interrupts: like its activity, priority level and number of automatically stacked registers.

Low energy for (not only) IoT

The D32PRO emphasizes low energy consumption, which is crucial in modern electronics. This is achieved thanks to special PMU (Power Management Unit), which dynamically controls the clock’s frequency. Thanks to it an engineer can program energy-saving mode for the CPU, where all the peripherals will be working with nominal clock. Moreover, the CPU itself can be moved to STOP mode with the clock detached from it. Then it can return to normal mode by an interrupt from any peripheral. In order to save additional power, the CPU can easily switch off the peripherals which are unused at the current moment.

Debugger – Bootloader

The D32PRO, similarly to DCD’s 8051 IP Cores, is delivered with a built-in hardware debugger. But this special solution has been tailored for 32-bit CPU, that’s why it enables full control from Eclipse level (complete Eclipse debugging system with GCC => USB 2.0 cable => D32PRO). Moreover, in DCD’s debugger only two pins have been used as optimal tradeoff between communication throughput and consumed resources, when in competitive solutions communication needs at least 5 pins (JTAG). Hardware bootloader unit enables firmware memory updates directly from external low cost Flash memory connected through the (Q)SPI interface. Moreover, the bootloader is equipped with hardware encryption mechanism which significantly protects firmware against reverse engineering.
More information: www.dcd.pl

Technical information:
DCAN-FD, CAN with Flexible Data Rate

DCAN FD, a Configurable CAN Bus Controller with Flexible Data-Rate targets autonomous cars & ADAS systems

 

Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has introduced the newest IP Core. The DCAN FD IP Core is a configurable CAN Bus controller with Flexible Data-Rate. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) in accordance to ISO 11898-1:2015. The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbps (even up to 8Mbps) and the payload (data field) is up to 64 byte long. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized.

Poland, Bytom, September the 26th, 2016. The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) – in accordance to ISO 11898-1:2015.

Standard CAN requirements become insufficient in modern automotive. The carmakers demand more bandwidth and more throughputs for most CAN-based in-vehicle networks. The DCAN FD IP Core is also a good alternative for non-automotive projects where not the increasing speed is the target. The longer payload (more than 8 byte) becomes crucial then.

The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbps (even up to 8 Mbps) and the payload (data field) is up to 64 byte long. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes need to be re-synchronized. – The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing scheme – explains Tomasz Krzyzak, VCEO in Digital Core Design. Hardware message filtering and 128 byte receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN FD is described at RTL level, allowing target use in FPGA or ASIC technologies.

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Information about Digital Core Design:

The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 75 times faster than the standard solution. The same, D32PRO, which is a royalty-free and fully scalable 32-bit CPU creates new possibilities for modern projects. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 500 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.