DCD-SEMI at SEMICON Taiwan 2026

Starting tomorrow, DCD-SEMI will take part in SEMICON Taiwan 2026, one of the most important semiconductor events in Asia.

From September 2 to 4, we will be present at TaiNEX in Taipei, inside the Poland Pavilion organized with the support of the Polish Investment and Trade Agency (PAIH).

Visit us at Booth I3116 to discuss how silicon-proven IP Cores from Poland can accelerate your next ASIC or SoC project.

At the booth we will present:

• CAN XL — automotive communication for next-generation and software-defined vehicles, with functional safety support up to ASIL-D
• RISC-V — 32-bit and 64-bit processors with peripherals and custom extensions
• A complete IP Core portfolio — more than 100 architectures already used in over 1 billion electronic devicesworldwide, including CPUs, cryptographic engines, and interfaces for FPGA and ASIC designs

Every chip starts with an idea.
DCD-SEMI turns these ideas into reality.

If you are in Taipei this week, come and meet us at the Poland Pavilion.

SEMICON Taiwan 2026
📅 September 2–4, 2026
📌 TaiNEX, Taipei
🟦 Booth I3116 — Poland Pavilion

See you in Taipei.

eSPI Combo for Next-Generation Intel-Based Platforms

DESPI eSPI Controller IP Core and DESPI eSPI IP Core Target deliver a complete, high-speed eSPI interface solution for FPGA and ASIC designs.

DCD-SEMI, a leading provider of synthesizable IP cores and SoC design services, today announced the DESPI eSPI Combo, a complete Enhanced Serial Peripheral Interface (eSPI) solution combining the DESPI eSPI Controller IP Core and the DESPI eSPI Target IP Core for high-performance FPGA and ASIC designs. Optimized for Intel-based embedded platforms and modern replacements of legacy LPC interfaces, the new combo enables robust host–target connectivity at up to 66 MHz over single, dual, and quad SPI links.

The DESPI eSPI Controller IP Core is a fully configurable eSPI host/controller, compliant with the eSPI Base Specification Revision 1.6  and designed for integration into complex SoC architectures. It provides a high-speed serial interface to Embedded Controllers (EC) and eSPI peripherals in Intel CPU platforms, ensuring low-latency communication and reduced pin count for space- and cost-constrained designs.

Complementing the controller, the DESPI eSPI Target IP Core operates as a configurable eSPI Target IP, also compliant with the eSPI Base Specification Revision 1.6. It supports single and multi-target configurations, making it ideal for ECs, peripheral devices, and multi-slave microcontroller systems that require reliable eSPI connectivity in demanding embedded and industrial applications.

“System designers working on Intel-based platforms want a clean, future-proof migration path away from LPC, without compromising bandwidth or reliability,” said Jacek Hanke, CEO of DCD-SEMI. “With the DESPI eSPI combo, we deliver both sides of the link: Controller and Target. As technology agnostic RTL that drops into any major FPGA or ASIC flow and scales from a single to complex multi-target systems.”

Both DESPI eSPI cores leverage a high-speed SPI interface capable of operating at serial clock frequencies up to 66 MHz, with support for single, dual, and quad SPI transfers to maximize bandwidth. Large, highly configurable shared memory buffer enables efficient and flexible frame and data storage to fit any needs.

The DESPI eSPI Combo supports customizable peripheral channels including memory-mapped I/O, Virtual Wire signals, event and alert signaling, and optional out-of-band and flash access channels. This flexibility enables precise tailoring of the eSPI fabric to application needs, from high-speed data acquisition and industrial control systems to embedded platforms where deterministic EC communication is critical.

“By offering a controller–target bundle, we simplify qualification and verification for our customers – they can prototype and validate their entire eSPI path using a single, silicon-proven IP family,” said Jacek Hanke. “Combined with our long-standing expertise in processor and peripheral IP, this gives SoC teams a fast, low-risk route to production.”

Both IP cores are delivered as technology-agnostic RTL, ensuring compatibility with all major FPGA and ASIC vendors and simplifying migration between prototype and production silicon. They are fully customizable at delivery, allowing customers to enable only the required channels and features to minimize area and power, while preserving a clear upgrade path for future products.

Typical use cases for the DESPI eSPI Combo include host interfaces for ECs in Intel CPU platforms, FPGA/ASIC-based SoCs requiring eSPI master functionality, high-speed industrial peripherals, and multi-target microcontroller architectures where low-latency, high-throughput communication is required. As a modern replacement for LPC, the combo supports next-generation embedded systems that demand higher integration, reduced pin count, and improved system throughput.

EdDSA Curve25519 IP Core Extension

DCD-SEMI expands CryptOne with EdDSA Curve25519 IP core for secure embedded systems

DCD-SEMI introduces a new CryptOne extension supporting EdDSA25519 signatures and X25519 key exchange, delivering high security, low latency, and efficient hardware implementation for modern SoC and FPGA designs.

Key highlights

• Hardware support for EdDSA25519 and X25519 based on Curve25519

• Optimized size-to-performance ratio for embedded and FPGA systems

• Built-in resistance to side-channel attacks

• Compliance with RFC 7748 and RFC 8032 standards

• Verified in simulation and FPGA environments

Advanced cryptography in hardware

DCD-SEMI has expanded its CryptOne cryptographic co-processor with a new EdDSA Curve25519 IP core, bringing hardware acceleration to widely used elliptic-curve cryptography. The implementation is based on Curve25519, a 255-bit curve known for its efficiency, compact arithmetic, and strong security properties.

The extension enables fast and reliable execution of X25519 key agreement and EdDSA25519 digital signatures, making it particularly suitable for secure communications in constrained embedded environments.

Optimized architecture for performance and efficiency

Unlike general-purpose processors, CryptOne is a configurable IP core tailored to specific customer requirements. The Curve25519 module integrates directly into the existing architecture through dedicated hardware instructions, modular arithmetic accelerators, and optimized control logic.

This design minimizes latency while reducing silicon area and energy consumption. By simplifying arithmetic operations and eliminating unnecessary branching, the implementation achieves predictable execution flow—an important factor for both performance and security.

Built with security in mind

The solution leverages Edwards-curve cryptography, which offers more regular computation patterns compared to traditional approaches. This reduces the risk of timing-based side-channel attacks and improves overall robustness in hardware implementations.

Alignment with industry standards, including RFC 7748 and RFC 8032, ensures interoperability and readiness for deployment in modern cryptographic systems.

Verified and deployment-ready

The development process included algorithm modeling, HDL implementation, and extensive verification using automated test environments. The IP core was validated against RFC-compliant test vectors and tested in simulation and FPGA setups to confirm correctness and optimization.

The result is a production-ready solution designed for security-critical applications across IoT, automotive, telecommunications, FinTech, cloud infrastructure, and industrial systems.

DCD-SEMI at Embedded World 2026

Let’s meet in Nuremberg during #EW26

Every chip starts with an idea… DCD-SEMI turns these ideas into reality.

The countdown is on – Embedded World Exhibition & Conference 2026 is only few weeks away, and we are ready to showcase the strength of Polish semiconductor innovation on one of Europe’s most important embedded technology stages.

Visit DCD-SEMI at Embedded World 2026

Hall 4, Booth 4-481
Come and meet our team, discover our latest developments, and explore how we deliver advanced IP and semiconductor solutions designed for the future of embedded systems.

Don’t Miss Our Conference Presentation

Embedded World Conference Series — IoT & Connectivity
10 March 2026
16:00
NCC Ost Convention Centre

Join us for an inspiring session where we will share insights into next-generation connectivity and innovation in the embedded world.

Get Your Free Ticket

Have you seen our “secret” code? Use it to claim a free visitor ticket and experience Embedded World firsthand: ew26567633

Innovation moves fast.
Safety, speed, and smart connectivity move even faster.

Let’s meet where ideas become reality.

See you in Nuremberg!

DCD-SEMI at SEMICON Korea 2026

DCD-SEMI to Exhibit at SEMICON Korea 2026 with EU Mission Hub

In less than a month, DCD-SEMI will take part in SEMICON Korea 2026, the largest semiconductor and technology trade show in the Republic of Korea. The event gathers key players from the global semiconductor ecosystem and underlines South Korea’s role as one of the world’s most advanced semiconductor markets.

The Republic of Korea ranks as Asia’s 4th largest and the world’s 12th largest economy and remains a global leader in semiconductor manufacturing. In 2023, it maintained its position as the world’s second-largest semiconductor producer for the 11th consecutive year, holding a 13.2% share of the global semiconductor market. The sector continues to expand rapidly, with semiconductor exports reaching a record €12.5 billion in April 2024, marking eight consecutive months of year-on-year growth.

SEMICON Korea serves as a strategic meeting point for IP vendors, chip designers, foundries, equipment manufacturers, and technology innovators from around the world. The 2026 edition will once again showcase the latest semiconductor technologies and create opportunities for international collaboration across the entire value chain.

DCD-SEMI will exhibit in the Business Exhibition area at Sono Felice, together with the EU Mission Hub – a European Union programme supporting the most innovative semiconductor companies and strengthening their global visibility. Participation under the EU Mission Hub highlights DCD-SEMI’s role as a trusted European technology provider and reinforces cooperation between the European and Korean semiconductor ecosystems.

During the event, DCD-SEMI will present its portfolio of advanced IP cores and custom semiconductor solutions for automotive, industrial, and embedded applications. The Business Exhibition at Sono Felice provides an excellent environment for technical discussions, business meetings, and the development of new strategic partnerships.

By exhibiting at SEMICON Korea 2026 alongside the EU Mission Hub, DCD-SEMI continues to expand its international presence and engage with partners in one of the world’s most dynamic and strategically important semiconductor markets.

We invite industry professionals to visit DCD-SEMI at the Business Exhibition at Sono Felice during SEMICON Korea 2026.

DI3CM-HCI, A High-Performance MIPI I3C Host Controller IP Core

DI3CM-HCI, A High-Performance MIPI I3C Host Controller IP Core for Next-Generation Embedded Designs.

Designed as a drop-in, higher-bandwidth, lower-power alternative to I²C and SPI, the DI3CM-HCI brings robust performance and scalability to designs that depend on increasingly dense arrays of sensors and actuators. The IP fully conforms to MIPI I3C Basic v1.1.1 and demonstrates general compliance with the MIPI I3C HCI Specification 1.1, making it ideal for SoC teams preparing for next-generation architectures.

“We’re seeing a clear shift in the industry toward I3C as the new baseline for intelligent peripheral connectivity,” said Tomek Krzyżak, CTO at DCD-SEMI. “The DI3CM-HCI provides the bandwidth, determinism, and power efficiency modern embedded systems require—while keeping integration as simple as possible for engineers.”

At up to 12.5 MHz operation, the DI3CM-HCI supports I3C SDR and HDR-DDR modes, while remaining fully backward compatible with I²C. Power efficiency is enhanced through optional clock gating, and throughput is optimized via configurable buffer sizes, programmable DAT/DCT structures, and a DMA handshake interface.

“Our goal was to give designers a controller that doesn’t limit them,” added Tomek Krzyżaki, CTO at DCD-SEMI. “Flexible FIFOs, customizable buffer depths, and ready-to-use bus wrappers reduce integration time dramatically—especially for teams working under tight schedules.”

Key Features:

• Full compliance with MIPI I3C Basic v1.1.1
• General compliance with MIPI I3C HCI Specification 1.1
• Up to 5 MHz clock frequency
• Support for I3C SDR and I3C HDR-DDR modes
• Legacy I²C communication compatibility
• Dynamic Address Assignment (DAA)
• In-Band Interrupts and Hot-Join
• Common Command Codes (CCC)
• Configurable FIFO and memory buffers
• Configurable DAT/DCT (up to 16 slots)
• DMA handshake interface
• Power-efficient design with optional clock gating
• Memory-mapped interface with available wrappers:
  • AMBA APB / AHB / AXI
  • Altera Avalon
  • Xilinx OPB

Engineered for Fast, Low-Risk Integration

To help teams accelerate project timelines, DI3CM-HCI ships with extensive documentation, synthesis scripts, reference implementations, and support options. Ready-to-use bus wrappers enable seamless deployment across FPGA prototypes and ASIC production environments.

“Engineers want solutions that just work,” said Krzyżak. “DI3CM-HCI removes the friction of adopting I3C and lets designers focus on building better systems—not fighting the interconnect.”

Target Applications

The DI3CM-HCI is optimized for designs where efficient peripheral communication, low power consumption, and tight latency control are critical. Key application domains include:

✔ IoT and Edge Devices

Ideal for sensor-rich platforms such as smart home hubs, environmental monitors, wearables, industrial IoT nodes, and battery-powered edge devices. I3C’s lower power profile extends device lifetime while maintaining high data integrity across multiple sensors.

✔ Consumer Electronics

Suitable for smartphones, tablets, AR/VR headsets, smart appliances, and human–machine interfaces where compact, high-throughput interconnects are essential for responsiveness and user experience.

✔ Automotive & Transportation Systems

Applicable in ADAS units, driver-monitoring systems, cabin environmental sensing, powertrain controllers, and safety-critical sensor clusters. Backward compatibility with I²C helps OEMs migrate legacy platforms without redesigning entire subsystem chains.

✔ Industrial & Robotics

Supports robotics systems, automation controllers, predictive maintenance sensors, and motor-control applications. The DMA handshake and configurable FIFOs ensure deterministic throughput even in real-time workloads.

✔ Medical & Health Monitoring Equipment

Suited for portable diagnostic devices, multi-sensor monitoring systems, wearable medical electronics, and equipment requiring low-noise, reliable sensor data streaming.

✔ FPGA- and ASIC-Based Prototyping

Thanks to its configurable interface wrappers (AMBA/APB/AHB/AXI, Avalon, OPB), DI3CM-HCI can be integrated into any SoC architecture, speeding up prototype development and reducing system-level risk.

Across all these segments, DI3CM-HCI enables engineers to replace slow, power-heavy legacy buses with a modern, synchronized, feature-rich interface that keeps pace with next-generation embedded system requirements.

More information: www.dcd-semi.com | Contact: info@dcd-semi.com

 

 

Ultra-Fast DAES IP Core for AES Encryption

Ultra-Fast DAES IP Core for AES Encryption

DCD-SEMI, a global provider of secure and high-reliability semiconductor IP, announces the launch of DAES IP Core, a high-performance hardware accelerator designed to bring lightning-fast AES encryption and decryption to today’s embedded, communication, and data-centric systems.

Supporting AES-128 and AES-256 across five major modes — ECB, CBC, CFB, OFB, and CTR — DAES delivers exceptional throughput while remaining easy to integrate into FPGA- and ASIC-based designs.

Hardware Acceleration for Real-World Performance

Engineered for maximum efficiency, DAES automatically manages data flow and performs hardware-level key expansion. This allows software to focus exclusively on I/O operations, significantly simplifying system architecture and eliminating common performance bottlenecks associated with software-based AES.

Its flexible memory-mapped interface supports the most widely used system buses, including AMBA (APB/AHB/AXI), Avalon, and OPB, ensuring fast, frictionless deployment in a wide range of SoC and FPGA platforms.

Performance Highlights

• Up to 7.68 Gbit/s throughput on AES-128 at 1 GHz

• Optimized for Xilinx Artix-7, Xilinx Virtex UltraScale+, and Intel/Altera FPGAs

• Configurable AES modes and key sizes to match system-level requirements

• Fully synthesizable and ready for ASIC or FPGA implementation

The DAES package includes Verilog RTL, testbenches, reference vectors, synthesis scripts, example C drivers, and complete documentation — all supported by DCD-SEMI’s engineering team.

With DAES, system designers can build faster, more secure products for communications, data storage, networking, edge devices, and embedded systems without compromising flexibility or performance.

Part of the Holistic DCD-SEMI Cryptography Ecosystem

DAES is a key component of CryptOne, DCD-SEMI’s comprehensive cryptography portfolio, which includes encryption engines, hash cores, public-key accelerators, TRNG modules, and security-oriented IP blocks.

Together, these solutions form a holistic, interoperable security ecosystem enabling complete end-to-end encryption architectures tailored to high-performance, high-reliability applications across communications, storage, industrial, and IoT markets.

Explore the ecosystem: https://www.dcd.pl/product-category/cryptography/

About DCD-SEMI

For more than 25 years, DCD-SEMI has delivered synthesizable IP cores enabling semiconductor companies and OEMs to accelerate product development and enhance system reliability. With over 5000 successful silicon implementations, DCD-SEMI technologies power solutions in automotive, industrial automation, communications, and IoT markets worldwide. The company specializes in secure, high-performance IP, offering advanced capabilities for functional safety, cybersecurity, and low-latency system design.

Meet DCD-SEMI at CAN XL China Road Show 2025

CAN in Automation (CiA) China Roadshow 2025
📅 November 18–21, 2025
📍 Beijing | Shanghai | Shenzhen

Join DCD-SEMI at the CiA China Roadshow 2025!

Discover how DCD-SEMI’s CAN IP cores are shaping the next generation of functional safety, low-latency, and high-bandwidth communication in automotive and industrial applications.

Our experts will present real-world implementations of CAN XL, highlighting how hardware-level optimization and ASIL-ready design can significantly enhance reliability and security across modern ECUs and embedded systems.

Hosted by CAN in Automation (CiA), this multi-city event brings together leading engineers, developers, and decision-makers to explore:

• The evolution from Classical CAN and CAN FD to CAN XL

• Functional Safety (ISO 26262) and CAN integration strategies

• Performance benchmarking and validation tools

• Next-generation IP solutions enabling safer, faster, and more connected vehicles

Meet the DCD-SEMI team to discuss how our automotive-proven IP cores—from CAN 2.0B and CAN FD to CAN XL—help semiconductor and system designers accelerate innovation while meeting the toughest automotive standards.

🔗 Learn more at: https://www.can-cia.org/services/education/technology-days/china-roadshow 

“Whether it’s a QM implementation for body electronics or an ASIL-D CAN XL controller for autonomous driving, our cores are ready,”
— Jacek Hanke, CEO, DCD-SEMI

👉 Meet us in China to discuss how DCD-SEMI can accelerate your next design.

Meet DCD-SEMI at Embedded World USA 2025!

🚀 Meet DCD-SEMI at Embedded World USA 2025!
📍 Anaheim Convention Center, Hall C – Level 1
📅 November 4–6, 2025

Talk directly with Nick Visic, Director of North America at DCD-SEMI, about our latest ASIL-D-ready automotive IP Cores — including the full CAN ALL family: Classical CAN, CAN FD, CAN XL, LIN, PSI5, and SENT.

💡 Now available as Safety Element out of Context (SEooC) for ISO 26262 functional safety up to ASIL-D, our automotive IP portfolio brings:

✅ Configurable safety levels from QM to ASIL-D
✅ Verified and third-party assessed cores
✅ Optimized ASIC and FPGA integration
✅ Reduced silicon area and design cost

“Whether it’s a QM implementation for body electronics or an ASIL-D CAN XL controller for autonomous driving, our cores are ready,”
— Jacek Hanke, CEO, DCD-SEMI

🔹 ASIL-D Safety. Real Design Freedom.
Our IP Cores feature hardware redundancy, diagnostics, ECC, CRC, and full safety documentation — helping OEMs and Tier 1s deliver mission-critical automotive systems faster.

👉 Meet us in Anaheim to discuss how DCD-SEMI can accelerate your next design.

Full ASIL-D Functional Safety to Entire Automotive IP Cores Portfolio

CAN ALL, our complete automotive IP Cores family — including Classical CAN, CAN FD, CAN XL but also LIN, PSI5 and SENT —is now available as Safety Element out of Context for ISO 26262 functional safety up to ASIL-D, the highest Automotive Safety Integrity Level.

This achievement means that all DCD-SEMI automotive IP Cores can be delivered with safety mechanisms tailored to customer requirements — from QM (Quality Management) versions without additional safety logic, through ASIL-B, up to ASIL-D. This flexibility allows automotive OEMs and Tier 1 suppliers to choose the optimal implementation for each specific function, reducing overdesign, silicon area, and cost while ensuring compliance with global safety standards.

“By reaching full ASIL-D readiness across our automotive IP portfolio, we give system architects and safety engineers complete freedom to define their safety targets,” said Jacek Hanke, CEO of DCD-SEMI. “Whether it’s a non-safety QM implementation for body electronics or an ASIL-D CAN XL controller for autonomous driving, our cores are ready — verified, checked by third party assessor, and optimized for both ASIC and FPGA flows.”

 

ASIL-D Safety for Mission-Critical Automotive Designs

ISO 26262 defines ASIL-D as the highest safety level required for life-critical automotive systems, such as ADAS, powertrain control, braking systems, and autonomous driving functions.

DCD-SEMI’s IP Cores implement end-to-end safety mechanisms that ensure compliance, including:

• Hardware redundancy support
• Safety monitors and diagnostics
• ECC-protected memories and buses
• CRC protection
• Integrated safety management interfaces
• Sophisticated failure detection mechanisms

The ASIL package is delivered with a complete Safety documentation including Safety Manual, FMEDA analysis, and supporting documentation required for customer safety cases and third-party certification processes.

 

Tailored Safety Levels – From QM to ASIL-D

The same IP Core can be configured at delivery to match the exact safety integrity needs of a given ECU:

• QM (Quality Management) – minimal footprint, no additional safety logic
• ASIL-B – standard safety measures for non-critical systems like infotainment or HVAC
• ASIL-D – highest safety integrity for braking, steering, or ADAS functions

This modular approach gives design teams fine-grained control over area, performance, and safety overhead, avoiding unnecessary complexity while accelerating time-to-market.

 

CAN XL – Ready for Next-Generation Vehicles

The portfolio includes support for CAN XL, the latest evolution of the CAN protocol, offering payloads up to 2048 bytes and data rates up to 20 Mbit/s, making it ideal for software-defined vehicles and zonal architectures.

Combined with ASIL-D readiness, this positions DCD-SEMI as one of the very few IP providers ready to support next-generation autonomous and connected vehicle designs. DCD-SEMI will be presenting its automotive IP Cores during China Road Show 2025 organized by CAN in Automation in Beijing, Shenzen and Shanghai (November 18-21, 2025).

 

 

 

 

 

Key Technical Highlights

• Full ISO 26262 ASIL-D readiness across Classical CAN, CAN FD, and CAN XL
• Configurable safety level: QM, ASIL-B, or ASIL-D per customer specification
• Delivered with Functional Safety Documentation and safety certification support
• Optimized for ASIC and FPGA implementation flows
• Built-in safety features: ECC, diagnostics, and fault handling
• Designed for ADAS, EVs, autonomous driving, and vehicle connectivity
• Scalable for zonal and software-defined vehicle architectures

DCD-SEMI at SEMICON West 2025 in Phoenix

From October 7–9, 2025, DCD-SEMI will participate in one of the most important events of the semiconductor industry – SEMICON West in Phoenix, Arizona.

Thanks to the cooperation with Invest in Pomerania, DCD-SEMI will be present at Booth 1982, showcasing its latest IP Core solutions dedicated to the semiconductor and automotive sectors.

Our company will be represented by Nik Visic, Director of North America, who will meet with customers and partners to present how DCD-SEMI’s IP Cores – developed for more than 25 years – support the creation of advanced SoCs, providing reliability, functional safety, and high performance.

Participation in SEMICON West is an excellent opportunity for DCD-SEMI to build new business relationships, exchange knowledge with industry leaders, and emphasize that every chip starts with an IP Core – and for a quarter of a century, those IP Cores have been delivered by DCD-SEMI.

📍 SEMICON West 2025
📅 October 7–9, 2025
📌 Phoenix, Arizona
🟦 Booth 1982

Meet DCD-SEMI at SEMICON Taiwan 2025

🌏 In just over two weeks, DCD-SEMI will join one of the most important events for the semiconductor industry in Asia – SEMICON Taiwan 2025.

We invite you to meet us at booth #L1116, where we’ll be showcasing:

🚘 CAN XL – the innovative automotive interface. DCD-SEMI is one of only three companies worldwide offering a validated and CiA-approved solution.
⚙️ RISC-V – 32-bit & 64-bit processors with peripherals and extensions.
🔗 A holistic IP Core portfolio – enabling the design of semiconductors for virtually any device.

Let’s talk about how our technology can empower your next ASIC or SoC project. See you in Taipei!

DCD-SEMI Joins MIPI Alliance and Unveils Latest I3C IP at MIPI Plugfest Warsaw 2025

DCD-SEMI, a leading provider of customizable IP cores and system-on-chip solutions, proudly announces its official membership in the MIPI Alliance, a global organization that develops interface specifications for mobile and mobile-influenced industries.

Joining MIPI Alliance marks a significant step in DCD-SEMI’s commitment to delivering industry-compliant, high-performance IP cores to its global customers. As part of this initiative, DCD-SEMI will showcase its latest I3C IP core during the upcoming MIPI Plugfest, held in Warsaw on June 23-24, 2025.

The new I3C IP core from DCD-SEMI is designed to deliver enhanced performance, lower power consumption, and simplified integration for next-generation embedded systems. Developed in line with the MIPI I3C® specification, the IP core supports seamless sensor integration and offers backward compatibility with I²C, making it ideal for use in consumer electronics, automotive, industrial, and medical applications.

“We’re excited to become a part of the MIPI Alliance and contribute to the development of globally adopted interface standards,” said Jacek Hanke, CEO of DCD-SEMI. “Our latest I3C IP core is a result of close alignment with the MIPI specification and offers unmatched flexibility and configurability for SoC and FPGA-based solutions.”

The MIPI Plugfest in Warsaw will provide a unique opportunity for DCD-SEMI to demonstrate the interoperability and robustness of its I3C IP in real-world test scenarios, alongside other industry leaders and MIPI members.

For more information about DCD-SEMI’s I3C IP visit the product page: https://www.dcd.pl/product/di3cm-hci/

Digital Core Design Unveils DPSI5 – The Next-Generation IP Core for PSI5 Communication

Digital Core Design (DCD), a leading provider of silicon-proven IP cores, proudly announces the launch of DPSI5, an advanced IP core solution designed for high-performance PSI5 (Peripheral Sensor Interface 5) communication. As a cutting-edge technology, DPSI5 offers enhanced efficiency, flexibility, and reliability for automotive, industrial, and safety-critical applications.

PSI5 is an industry-standard interface widely used in modern vehicles and industrial automation systems, providing robust sensor communication in demanding environments. With the introduction of DPSI5, Digital Core Design takes PSI5 communication to the next level, delivering a fully customizable and optimized IP core that meets the stringent requirements of automotive and industrial applications.

Key Features of DPSI5:

• Comprehensive PSI5 Support: Fully compliant with the PSI5 standard, ensuring seamless integration with existing and future sensor systems.
• High-Speed & Reliable Communication: Optimized for real-time data transfer with minimal latency and maximum reliability.
• Flexible Configuration: Supports multiple communication modes and can be easily adapted to specific project requirements.
• Low Power Consumption: Designed for energy-efficient applications, making it ideal for automotive and industrial environments.
• Scalability & Customization: Can be tailored to meet the needs of different implementations, offering unmatched design flexibility.

DPSI5 is a crucial part of the industry’s most holistic automotive solution, CAN ALL, which comprises a set of the handiest and silicon-proven automotive IPs: CAN 2.0, CAN FD, CAN XL, LIN, SENT and PSI5. This comprehensive suite ensures seamless integration and interoperability across various in-vehicle communication protocols, enabling manufacturers to develop next-generation automotive systems with confidence.

 

“The launch of DPSI5 marks another milestone in our commitment to delivering state-of-the-art IP solutions for modern embedded systems,” said Jacek Hanke, CEO at Digital Core Design. “With its high performance, reliability, and adaptability, DPSI5 empowers engineers to build smarter and more efficient automotive and industrial applications.”

DCD’s DPSI5 is now available for licensing, offering a ready-to-use solution for companies looking to integrate PSI5 communication into their next-generation products. For more information, contact our team at info@dcd.pl

D68000-CPU32+ for well-known 68k family

DCD’s latest IP Core is a modern incarnation of CPU32+ based on M68020, which are no longer available, yet still in use in millions of projects. What differs D68000-CPU32+ from other similar solutions is automatic byte alignment feature that is not available in CPU32. This feature allows both 16 and 32-bit data to be transferred at any odd addresses. The CPU32+ automatically adjust required bus cycles and if it’s not enough, it operates also on 32-bit external operands with one bus cycle.

 

The engineering team at Digital Core Design in Poland have introduced the newest version of the classic MC68020 based 16/32-bit microprocessor. The D68000-CPU32+ is the industry’s low cost 32-bit MCU, offering a low-cost entry point combined with effective performance.

The CPU32+, an enhanced version of the classic 68020, is designed to seamlessly replace outdated CPU32+ components that are no longer available in the market. The D68000-CPU32+ serves as an ideal solution for systems with existing CPU32+ architecture.

Key Features of the D68000-CPU32+ include:

• Versatile Data Bus Transfers: The CPU32+ supports 8-, 16-, and 32-bit data transfers on the bus to any address, including Byte misaligned addressing, providing unparalleled flexibility in data handling.
• Dynamic Bus Sizing: The IP core incorporates dynamic bus sizing for byte and word, allowing for efficient and adaptive data processing tailored to specific application requirements.
• 32-Bit Data and Program Bus: With a 32-bit data and program bus, the CPU32+ ensures enhanced performance and seamless integration with modern systems, while maintaining compatibility with legacy components.
• Extended Memory Support: The D68000-CPU32+ is engineered to support up to 4 GB of both data and program memory, meeting the demands of contemporary applications with expansive memory requirements.

“The D68000-CPU32+ represents a significant leap forward in our commitment to providing robust solutions for legacy systems,” said Tomasz Krzyżak, CTO at Digital Core Design. “This IP core not only ensures the continued operation of systems reliant on CPU32+ architecture but also introduces advanced features to meet the evolving needs of our clients.”

Digital Core Design remains dedicated to delivering cutting-edge solutions that bridge the gap between legacy technologies and the demands of modern computing. The D68000-CPU32+ is poised to become an indispensable component for engineers and developers seeking a reliable and efficient replacement for obsolete CPU32+ based parts.

For more information on the D68000-CPU32+ and other innovative products from Digital Core Design, please visit https://www.dcd.pl/product/d68000-cpu32-plus/.

AES XTS IP Core for ligtweight cryptography

Digital Core Design Presents DAES XTS Cryptographic CPU for Unparalleled Security

 

DAES XTS IP Core from Digital Core Design is a compact cryptographic co-processor designed for seamless implementation of the Rijndael encryption algorithm in compliance with FIPS 197 Advanced Encryption Standard, specifically in XTS mode (in accordance with IEEE Std 1619-2007 standards.

 

[Bytom, December the 12^th, 2023] — DCD, a leading innovator in cryptographic solutions, proudly announces the launch of the DAES XTS, a revolutionary lightweight cryptographic co-processor. This advanced hardware is meticulously designed to seamlessly implement the Rijndael encryption algorithm in compliance with FIPS 197 Advanced Encryption Standard, specifically tailored for XTS mode as per IEEE Std 1619-2007 standards.

• The DAES XTS IP Core addresses the critical need for robust hardware disk encryption in IoT and embedded devices applications – says Jacek Hanke, DCD CEO – With a specialized focus on supporting encrypted memories such as FLASH or RAM, the co-processor features a unique random data access block function, making it an optimal choice for securing sensitive data.

Deploying the widely recognized AES block cipher, the DAES XTS offers unmatched security and performance benefits over software-based solutions. Its hardware-centric design positions it as a key player in securing environments ranging from IoT devices to cloud servers.

It is important to highlight that, in its current state, Ciphertext-Stealing mode is not supported. Therefore, users should ensure memory sectors are aligned to multiples of 128-bit blocks when implementing the DAES XTS.

Additionally, the DAES XTS seamlessly integrates with a diverse range of SPI memory controllers, enhancing its adaptability and compatibility across various applications. This strategic integration amplifies the co-processor’s effectiveness and broadens its application scope.

DCD continues to push the boundaries of cryptographic innovation with the launch of the DAES XTS, reinforcing its commitment to delivering cutting-edge solutions for enhanced data security in today’s interconnected world.

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

CAN FD Full

CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL. It is called “CPU friendly” because it efficiently relieves it through configurable registers and… few additional innovations.

DCD’s CAN FD FULL IP Core is a versatile and adaptable solution for incorporating Controller Area Network (CAN) functionality into various systems. This IP module can be implemented independently, as a part of an ASIC, or FPGA. It adheres to the ISO11898-1:2015 standard, enabling seamless communication in accordance with popular industry protocols.

DCD’s CEO, Jacek Hanke, inquires about the rationale behind labeling it as “CPU friendly.” – This distinction can be attributed to its enhanced filtering capabilities, which effectively alleviate the strain on CPU resources. By swiftly directing crucial messages to the buffers, they are promptly received without delay. Conversely, less critical data, such as temperature instructions, are stored in a FIFO (First-In-First-Out) arrangement. Once the FIFO reaches its capacity, all the accumulated messages are then transmitted to the CPU.

This module provides support for both Classical CAN and CAN FD but to establish a physical connection to the CAN bus, external transceiver hardware is required. DCD’s solution utilizes a single or dual-ported Message RAM, which is located outside of the module itself. This storage medium is connected to the CAN FD Full through the Generic Master Interface, facilitating efficient message handling.

The Host CPU can easily connect to the CAN FULL IP Core module via the 32-bit Generic Interface, enabling seamless integration and streamlined data exchange. DCAN FD Full supports all popular wrappers available on the market like e.g.

• AMBA – APB / AHB / AXI Lite Bus
• Altera Avalon Bus
• Xilinx OPB Bus

The IP core is available in two versions – Basic and Safety-Enhanced.

The DCAN FD Full has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and be provided together with detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step by step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.

This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD-SEMI may optionally deliver higher ASIL level ready IP. For further information and the optional features please contact our support.

More information: https://www.dcd.pl/product/can-fd-full/

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

DFSPI IP Core from DCD supports all serial memories available on the market.

Digital Core Design, the leading IP Core provider and System-on-Chip design house presents its latest DFSPI IP Core for access to NOR and NAND Flash Devices. And if universal NOR & NAND Flash IP is not enough… DCD’s DFSPI IP Core also supports MRAM, pSRAM, DRAM, and EEPROM – combining ease of use with reliability, low power, and speed under all conditions, including automotive, industrial, and other applications.

DFSPI IP Core is a real “combo” between all SPI IP Cores available on the market – it’s an SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL, QUAD, OCTAL SPI Bus Controller with DDR / DTR support and optional AES Encryption) + NOR & NAND Flash Memory Support for all serial memories available on the market.

– As an option, the DFSPI controller has built-in support for HyperBus^TM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification – explains Jacek Hanke, DCD CEO The same the SPI Controller allows easy communication with all available SPI FLASH memories.

The DFSP IP Core is compatible with the xSPI JESD251 standard, which can be accessed through a standard AXI4 slave interface. It offers backward compatibility with Octal SPI, QSPI, DSPI, and SPI interfaces. Furthermore, it supports the JEDEC SFDP Standard. The IP allows users to quickly access memory from the xSPI device in SPI mode. Alternatively, users can issue a command to switch to a different mode. Additionally, a DMA command can be used to copy memory from the xSPI device to any other location on the bus.

The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface with higher-performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, delivering it in the exact configuration that meets users’ requirements.

DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. These cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

More information: https://www.dcd.pl/product/dfspi/

 

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

One solution for complex CAN architectures

DCD provides the DCAN FD IP core for the implementation of standalone CAN (FD) controllers. The company’s CAN-All ecosystem considers automotive safety standards and expands towards CAN XL.

 

More detailed information can be found in CAN in Automation Newsletter and webpage: https://can-newsletter.org/uploads/media/raw/9b65ce48915450ad8463848124762907.pdf

Enhanced Serial Peripheral Interface (eSPI) Master/Slave Controller

The eSPI bus is an LPC bus improvement. The serial clock line (_sck) synchronizes shifting and sampling of the information on the IO lines. – It is a technology-independent design that can be implemented in a variety of process technologies – explains Jacek Hanke, DCD-SEMI CEO.

The DESPI is flexible enough to interface directly with numerous peripherals. The system may be configured either as master or as slave, and depending on the core configuration, the _in or _out lines will be utilized. Its serial clock can run up to 66MHz – adds Hanke.

The DESPI is also capable of simple, dual, and quad SPI transfers. The DESPI is fully customizable, which means it is delivered in the exact configuration with the target design requirements. Additionally, the DESPI module is equipped with receiver and transmitter FIFOs, capable of storing up to 4096+16 bytes (Header and maximal data payload) in separate buffers for every eSPI channel. (Peripheral Channel Posted and Non-Posted, Virtual Wire Channel, Out of Band Channel, Flash Access Channel).

The controller is capable to operate in several eSPI configurations:

• Single Master- Single Slave,
• Single Master – Multiple Slaves.

The DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. The DCD SPI cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

More information: https://www.dcd-semi.com/product/despi/

DCD adds extra features to LIN IP Core and GuardKnox license the solution

DCD, a leading IP Core provider and SoC design house from Poland, mastered the unique LIN IP Core with UART half-duplex enhanced functionality. The newest Core conforms to ISO17987-6:2016 protocol conformance test specification for Functional Safety. GuardKnox, an Israeli-based company with subsidiary locations in Munich, Germany, and Detroit, Michigan –integrated DCD’s LIN IP Core as part of their CommEngine product– a holistic solution for communication routing and switching capabilities.

DCD’s LIN IP Core’s been developed as ISO26262 Safety Element out of Context (SEooC). – It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation – says Jacek Hanke, DCD’s CEO – we also added another handy feature to this LIN IP Core – UART half-duplex enhanced functionality.

The IP core is available in two versions – Basic and Safety-Enhanced. The second has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instructions to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.

SPI: These Three Letters Denote Everything You Asked For

Electronics are everywhere. Many times, as frequent users, we do not even notice a “paradigm change” in the things we use on regular basis. We use a fridge, but we do not care that there is a microcontroller (MCU) and a set of sensors instead of a basic thermostat. We use a tablet with a touchscreen, but we do not care how the screen-tap information is transmitted to the MCU. We use SD cards to store photos and movies in our smartphones, cameras, and other portable devices, but the card’s interface is a big mystery for many — at least for those who have never dug into the details.

Every electronic device must be equipped with an MCU — also called the device’s brain. An MCU is a tiny computer fabricated on a single chip. It contains at least one central processing unit (CPU), memory, and input/output peripherals. When we talk about peripherals, the serial peripheral interface (SPI) becomes crucial. SPI plays an essential role enabling fast, reliable, and simple short-distance communication. It is also simple enough to implement and has a low resource usage. This is reflected in the statistics: EE Times Asia shows the most popular MCUs, and each and every one of them is equipped with SPI controller; the same in Electronics-Lab.com’s ranking and other rankings. So it’s obvious that SPI is a must for every MCU.

This article focuses on the most important details of the modern SPI interfaces, which are improved by many useful features. But to start, let us discover the history of the modern SPI interface, because even the old, most basic SPI interfaces are still in use.

Brief history

SPI was developed by Motorola in the 1980s. It is a synchronous serial communication interface used in embedded systems. The single SPI specification (the first specification) describes the master-slave architecture (full-duplex), typically with one master device and multiple slave devices. It is also called the four-wire serial bus:

• SCK — serial clock line (master output)
• nSS — slave select line, active on low logic level (master output, one for each underlying slave)
• MISO — serial data line: master in, slave out (master input, slave output)
• MOSI — serial data line: master out, slave in (master output, slave input)

Why did SPI become so popular? Mainly because of its simplicity. There are no start nor stop bits, there is no parity like in UART bus, and it enables higher transfer rates than I²C. There are plenty of pros.

The logic resources needed to implement SPI are very few: Single SPI simultaneous transmission and reception synchronized by serial clock can be modeled as two shift registers in a loop, as it has been presented below.

In reality, the SPI controller internal architecture is much more complicated than it has been shown in Figure 1, featuring more control registers, port control logic, and interrupt control. The example architecture can be found in Motorola’s SPI standard, “SPI Block Guide.”

The clock phase and polarity are configurable. There are four transfer formats available:

CPOL defines whether SCK is low (0) or high (1) when bus is idle (nSS is high).

CPHA defines whether the first (0) or second (1) SCK edge after nSS has been asserted (nSS is low) is used to sample data.

If data is sampled at the rising SCK edge, then shift occurs at the falling SCK edge.

If data is sampled at the falling SCK edge, then shift occurs at the rising SCK edge.

The shift registers are both 8 bits (in master and in slave). Data is shifted out with the most significant bit first and shifted in with the least significant bit first. The transmission is full-duplex because both the master and slave send and receive data simultaneously.

MISO and MOSI lines can be combined into one bidirectional line, but the transmission will be reduced to half-duplex. In this case, only three wires are needed for SPI transmission/reception.

There are many implementations of SPI bus controllers available on the market. Just as an example, DCD-SEMI’s DSPI is a fully configurable SPI master/slave device. It is flexible enough to interface directly with numerous standard peripherals like memories, sensors, etc. The IP is easy to use and utilizes a low amount of logic resources — just as the SPI should be.

Multi-line SPI

SPI is frequently used in communication with serial memories. The memory size can be large, which enforces the need of faster transfers. SCK cannot increase infinitely, so the first thought is to increase the number of data lines, not to unnecessarily increase the number of wires. it is better to stay with the half-duplex transmission.

As the first, dual SPI has been introduced. MOSI has become SIO0 (Serial I/O 0) and MISO has become SIO1. SIO0 carries even bits and SIO1 carries odd bits. The bus throughput becomes doubled.

Then the quad SPI has been mastered. New data lines have been added: SIO2 and SIO3. The bit transmission scheme looks as follows:

The bus throughput becomes doubled again, and each data byte can be sent in only two SCK cycles.

The SPI transfer from/to serial memory consists of several phases: Instruction (command), Address, Data, and, optionally, Checksum. Some commands are required to be sent in single SPI mode, while Address and Data are sent in multi-IO mode.

Further extending quad SPI, some devices increase the transfer rate by using double-data–rate (DDR) transmission, wherein data lines are sampled both on the rising and falling edge simultaneously, so every data byte is sent in just one SCK cycle. An example is shown in Figure 5.

One could ask: If we are already using four data lines, why not expand further? So thought the engineers who introduced octal SPI. In single-data–rate (SDR) mode, 1 byte is sent in one SCK cycle, and in DDR mode, 2 bytes are sent in one SCK cycle. The bandwidth increases significantly. An example is shown in Figure 6.

The transfer format shown in Figure 6 has its limitations. Instruction is sent repeated, as 2 bytes, to preserve an even number of bytes in transfer, because sampling is done on every SCK edge. Alternatively, the command can be sent in SDR mode. Address and Data phases must also contain an even number of bytes.

By now, the CPOL and CPHA settings have lost their meaning. Octal SPI DDR transfers are conducted only in SPI mode 0.

For HDL designers, it’s common to develop backward-compatible SPI master/slave controllers. DCD-SEMI finds customer’s interest in the DQSPI that supports single, dual, and quad SPI transfers, while DOSPI supports single, dual, quad, and octal SPI transfers. Both support DDR transfers, support multiple SPI slaves, implement a dedicated FIFO memory, and are available with the most common CPU bus interfaces. In single SPI mode, all of Motorola’s SPI configurations are supported.

eXecute In Place

Thanks to DDR and quad/octal transfers combined with high SCK frequency, it became possible to execute programs directly from a serial memory instead of copying the program memory into RAM. The program code must be stored in nonvolatile memory and the serial flash memory is cheaper than a parallel. The SPI controller in eXecutive In Place (XIP) mode is considered a bus bridge: From the “CPU’s point of view,” it is a simple memory that can be accessed parallel, and from the “SPI memory’s point of view,” it is just an ordinary SPI master. The CPU read transfers are performed with zero latency, if the program is executed linear (address after address) or the jump does not cross boundary of memory page, stored in controller’s FIFO memory. Also, in a typical embedded system, the MCU does run on significantly lower frequency than the SPI controller, so the data is available immediately, even if the next memory page has to be read.

In XIP mode, there is also available the regular register access to SPI controller. This mode is also used to configure the IP’s internal registers.

Typically, XIP is used in First Stage Boot Loader, e.g., in embedded systems, Linux OS, BIOS, etc. The SPI controller is preconfigured on power-on reset, and after the reset is deactivated, it starts reading the first memory page. There are also attempts to prepare file systems based on XIP.

The aforementioned DQSPI/DOSPI, as well as the latest SPI flash controller (DFSPI) are also available with the XIP interface. This ensures optimal system performance and wide configuration options.

Recently, another interesting feature can be found in SPI controllers, like in the DFSPI. For best performance and lowest software overhead, the automatic configuration feature can be used. The SPI controller is equipped with additional small memory, which acts as the lookup table, storing predefined device configuration. The memory content is prepared before the synthesis and implementation, or in a more advanced solution, it can be modified like an ordinary internal register. After writing Instruction/Command into the SPI controller, the device is automatically configured. The configuration may cover:

• Command code
• Addressing mode
• Transfer type — transmission or reception
• Latency/dummy cycles
• SPI mode: single, dual, quad, octal
• SDR/DDR
• Other

eXpanded Serial Peripheral Interface

Based on the information from this article, we can see how handy SPI is. JEDEC created a new standard above SPI, with limited backward compatibility. The standard defines commands for general-purpose read and write of any device, which helps in system development. eXpanded Serial Peripheral Interface (xSPI) helps to develop device-provider–independent applications.

xSPI enables flexible configuration of SPI transfer mode (single, dual, quad, octal) and SDR/DDR mode. Instruction, Address, and Data can all be independently performed in one of the modes as follows:

• Instruction phase — Address phase — Data phase
• Width (number of data lines used)
  • 1: SIO0
  • 4: SIO0, SIO1, SIO2, SIO3
  • 8: SIO0, SIO1, SIO2, SIO3, SIO4, SIO5, SIO6, SIO7
• Data rate options: S for SDR, D for DDR

For example, a 4S-4D-4D can be performed.

HyperBus became part of xSPI in 2017. It has been named xSPI type 8D-8D-8D Profile 2.0.

In both HyperBus and xSPI, high clock rates can be achieved by using a separate clock signal for transmission (master-generated) and for reception (slave-generated/returned with internal delay). This provides best timing reference and is source-dependent. The data and strobe must be synchronous, while the strobe and SCK have no phase dependency.

The DFSPI is one of the SPI controllers already supporting xSPI.

It’s worth mentioning that recently, a new Xccela Consortium has been established. The new standard is xSPI-compliant at the physical layer. It focuses on the plug-and-play compatibility between products and provides complete device specifications and guidelines for designers.

Serial bus replaces parallel bus

Enhanced Serial Peripheral Interface (eSPI) uses the same timing and electrical requirements as regular SPI, but it is designed to replace the deprecated LPC bus, which has replaced the ISA bus on the PC’s motherboard. The LPC messages and much more are replaced by in-band SPI transfers. eSPI is low-power, energy-efficient, and configurable bandwidth bus. Even though at the physical layer, the eSPI uses the same SPI bus, the protocol and requirements are different.

First of all, eSPI introduces a new signal “alert,” which works like an interrupt request from the slave to the master. If the master asks for data and the data cannot be immediately returned, the transmission is ended and the slave requests transmission completion after the data has been prepared. Alert can only be driven when bus is idle (CS is high).

Each eSPI transfer consists of a Command and Response phase divided by a Turnaround phase. In Command, the master drives information on the bus. In Turnaround, all I/O lines are tri-stated, and the bus mastering is given to the slave. In Response, the slave drives information on the bus. Both Command and Response are supervised by CRC. In Response, the eSPI slave also returns the internal slave status register state.

Without going deeper into the details of the eSPI bus, we can see how different it is — also a good example of the usage of the SPI bus. xSPI gathers all the previous SPI standards together, while eSPI is a totally different standard. eSPI has been created by Intel and is best tailored for motherboards with Intel CPU (Intel architecture Skylake U or newer).

eSPI standard goes back to 2016. As we can see in different vendors’ portfolios, it is not so common like xSPI, but DCD-SEMI has already got a dedicated DESPI controller available.

Summary

SPI has evolved over the last four decades — from a basic concept to an advanced serial bus. But one thing remains the same: It is commonly used and can be found everywhere. But before you use an SPI controller in your next project, it will be worthwhile to compare the available IPs and to choose the best-fitting one in your design. As an example, you can take a look at the table below. All SPI IP cores, but the functionality differs a lot.

SHA IP Core with native SHA2-256 HMAC support

Our latest DSHA2-256 IP Core is a universal solution which efficiently accelerates SHA2-256 hash with native HMAC mode. This IP targets authenticity and data integrity verification in digital signature protocols and all aspects of secured communication. It’s worth to mention that due to its unique features, the DSHA2-256 IP Core might also be used in crypto currency computations acceleration.

The DCD’s DSHA2-256 is a universal solution which accelerates SHA2-256 hash function compliant with FIPS PUB 180-4. It computes message digest either in 256 and 224 bit modes. Allowed input message length is up to 2⁶⁴ – 1 bit. The core is fully configurable, which significantly reduces design time. – Native support of the SHA2-256 HMAC (keyed-Hash Message Authentication Code) is a… key – says Jacek Hanke, DCD’s CEO – this cryptographic function defined in RFC 2104 is a must in all kinds of secured communication.

The DSHA2-256 is suitable for authenticity and data integrity verification in digital signature protocols and all other communication where security is the key. It might also be used in crypto currency computations accelerating. DCD’s IP Core offers context swapping feature which is extremely useful in complex systems with a task’s preemption mechanism and software managed or custom HMAC scheme.

SHA2 is a family of cryptography secure one-way compression functions based on Merkle-Damgard structure, the 256 version sequentially process 512 bit input blocks during 64 rounds. From arbitrary length input message (maximum 2⁶⁴ – 1 bits) it produces fixed 256 or 224 bit length digest in a way that it is practically infeasible to invert it (get original message from its digest). Such property is called a one-way function.  Cryptographic security of SHA2-256 is assumed at 128 bit level (112 bit in case of SHA2-224) which makes it appropriate to use in security applications. Some of them need to prove knowledge or possession of some secret data while computing message digest. For such authentication purpose the HMAC function has been designed. It combines both secret key and cryptography secure hash function (like SHA2-256).

Key features:

• FIPS PUB 180-4 compliant SHA2-256 function
• RFC 2104 compliant HMAC mode native support
• SHA2 224 and 256 bit modes support
• Secure storage for precomputed HMAC keys
• Hash/HMAC context swapping
• Internal, automatic padding module
• Binary message resolution support
• Flexible data read/write modes
• AMBA AHB, AXI4, APB interface ready
• Software support:
  • Software driver with OpenSSL/MbedTLS interface ready
• Applications
  • Digital signature
  • Data integrity
  • Key derivation
  • TLS/SSH/PGP IPsec communication

Applications

• Digital signature
• Data integrity
• Key derivation
• TLS/SSH/PGP IPsec communication

Deliverables

The list of deliverables consists of:

• Source code:
  • VERILOG Source Code
  • Software driver in C with OpenSSL/MbedTLS interface ready
• VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
• Technical documentation
  • HDL core specification
  • Software driver documentation
• Synthesis scripts
• Example application
• Technical support
  • IP Core implementation support
  • 3 months of maintenance
    • Delivery the IP Core updates, minor and major versions changes
    • Delivery the documentation updates

The Most Innovative IP Core of the Year 2019

CryptOne, DCD’s latest cryptographic IP Core, has been awarded with “2019 Most Innovative IP of the Year” by Design & Reuse during IP SoC Days in Shanghai, China. 

IP SoC Day has ben organised in September the 19th, 2019 by Design&Reuse in Shanghai, China. More than 25 well know IP Core & SoC companies decided to present their products during the show and several hundreds of other – to participate.

Here’s detailed program: http://www.design-reuse-embedded.com/ipsocdays/ipsocdays2019/china2019/#

Just 10 from these companies have been nominated for “The Most Innovative IP Core of the Year” Award. Among them Digital Core Design with our latest CryptOne IP Core. 100% safe cryptographic system got the biggest attention (and votes, thank you!) which denotes our WIN!

If you’re curious about the winner and the best runner-ups, here’s the link: http://www.design-reuse-embedded.com/ipsocdays/ipsocdays2019/china2019/files/bio/BestPrize.jsp#

DCD is celebrating 20th Anniversary

More than 500 000 000 electronic devices around the globe have been based on DCD’s IP Cores. Among them one can easily find YOUR solution. Taking the chance we’d like to thank you for our hitherto cooperation, cause this 20th anniversary for DCD wouldn’t be possible without you.

Taking the chance to thank you, we’ve prepared some gifts for you. First one is our summer promo – 20% off from the IP Core price for 20th anniversary. Sarting from June till September you can easily license any of our IP Core with great discount. No matter if it’s 32-bit royalty-free CPU, I3C or World’s Fastest 8051 IP Core – they’re all here, waiting for you and your project. Just drop us an e-mail and let us know what you need.

The second one is our… knowledge. That’s why, taking the chance, we’ll be publishing some of our best case studies from last 20 years. First one is here: http://mailchi.mp/77bf92df4dd1/cryptographic-ip-core-system

And last but not least – please remember, we’re here for you! Let us know by e-mail, social media, phone what can we do for you.

 

Meet us at Hannover Messe 2019

DCD unveils CryptOne cryptographic system

 

Digital Core Design, celebrating 20th anniversary in 2019, mastered a completely new and innovative cryptographic systeme. Basing on two decades of IP Core market experience and best Polish cryptographers solutions, DCD’s programmers introduced:

CryptOne, a 100% safe cryptographic system.

What is the top concern for developing IoT solutions? 39% of the answers stated: security (Copyrighe 2018, Eclipse Foundation, Inc.). That’s why Digital Core Design decided to create an innovative cryptographic system which will boost encryption & decryption performance. Eager to know more? Join us in Hannover, Germany starting from April 1st till 5th. Official press conference will be held on Monday, 1st of April at Polish National Booth (Hall 27, H12) – 12:00 CET.

 

 

 

CryptOne – 100% safe crypto CPU IP Core

CryptOne IP Core involves the use of RSA asymmetric encryption scheme to realize a cryptosystem with a one-time pad (OTP). DCD’s solution is a broadly defined crypto system solution based on an asymmetric RSA with a hidden value of a component of a public key susceptible to crypto analysis and implementing the OTP rules.

Nowadays security is the key. That’s why CryptOne OTP offers the advantages of symmetric crypto systems with one-time pad while retaining the advantages of asymmetric systems. Our crypto system will enable the realization of unconditional security while eliminating OTP distribution problems and providing an unambiguous identification of users. – It should be emphasized that the current requirements for cohesive solutions for the European Union and e-services-like systems, as well as for sensitive data industry such as e-health and e-banking, necessitate the use of unambiguous and unique to each user identifiers that correspond to OTP – says Jacek Hanke, DCD’s CEO.

More information coming soon…

Eager to know more? Drop us an e-mail.

DI3CM-FIFO IP Core compliant with MIPI I3C v1

IP Core provider and System-on-Chip design house from Poland introduced the DI3CM-FIFO IP Core. It incorporates all features required by the latest MIPI I3C specification. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance.

Bytom, December the 5th, 2017. The I3C (Improved Inter Integrated Circuit) is the next generation of the I2C. Keeping the best assets from its elder brother, the I3C offers major improvements in terms of use, power consumption and performance. The Core uses just two pins and consumes a fraction of energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced to a controller or application processor.

Digital Core Design maintains backward compatibility, to enable a smooth transition from I2C to I3C and focus on simple implementation. – The DI3CM-FIFO offers a flexible multi-drop interface between the host processor and peripheral sensors to support the growing usage of sensors in embedded systems – explains Piotr Kandora, Vice President of Digital Core Design.
The I3C interface uses an I2C-like interface with data line (SDA) and clock line (SCL). The open drain SDA line allows for slaves to take control of the data bus and initiate interrupts. The push-pull SCL line is used by the master to clock the communication bus up to 12.5 MHz. The master can dynamically assign 7-bit addresses to all I3C devices while supporting the static addresses of legacy I2C devices. This ensures full compatibility between MIPI I3C and I2C. The Core represents a shift in power performance while providing greater than an order of magnitude improvement in speed over I2C. I3C offers four data transfer modes that, on maximum base clock of 12.5MHz, provide a raw bitrate of 12.5 Mbps in the baseline SDR default mode, and 25, 27.5 and 39.5 Mbps, respectively in the HDR modes. After excluding transaction control bytes, the effective data bitrates achieved in each mode are 11.1, 20, 23.5 and 33.3 Mbps, respectively, protected by I3C’s basic error detection mechanisms.
The I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, high-speed and other critical features that are currently covered by I2C and SPI.

Key features:

• conforms to MIPI I3C v1.0 specifications
• MIPI Manufacturer ID: 0x03B3
• Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
• Legacy I2C messaging
• I2C-like Single Data Rate messaging (SDR)
• Master operation with FIFO:
  • Master transmitter
  • Master receiver
• Supports flexible transmission speed modes:
  • FAST-PLUS (up to 1000 kb/s)
  • SDR (up to 12,5 Mb/s)
• Configurable FIFO size up to 256 Bytes
• Configurable SDA/SCL glitch filter
• Software programmable SDA/SCL bus timings
• Multi-master systems supported
• Interrupt generation
• Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
• Configurable interface allows easy connection to standard bus interfaces: APB, AHB, 8051, 80251, others
• Support for in-band interrupts
• Support for I3C common command codes
• Dynamic address assignment (DAA) support
• Command queue support
• Low power management support
• Fully interoperable with third-party I3C master and slave solutions
• Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset

DUSB2-ULPI, an USB 2.0 device controller with ULPI interface

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.

D32PRO, fully scalable and royalty-free 32-bit CPU

The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz. The minimal usable D32PRO CPU starts from 10.6k/6.8k gates when optimized for area. Dynamic power is 7 microwatts/MHz with a 90 nm process (DCD’s IP Cores are synthesizable and foundry independent). The D32PRO has been equipped with C compiler and integrated CPU configurator. This makes DCD’s CPU fully configurable, both for ultra-low energy and for power-user projects.

The D32PRO is a deeply embedded, royalty-free 32-bit CPU. Drawing on its valuable experience – like the world’s fastest 8051 – Digital Core Design created completely new, RISC 32-bit CPU. This silicon proven CPU enables engineers to tailor it to their needs – The D32PRO is fully scalable, hence it can be easily adjusted to get the efficiency comparable to ARM Cortex M0-M3 – explains Tomek Krzyzak, DCD’s vice-president – but there’s no problem to run the Core with maximal performance to get up to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz.
The D32PRO has been designed from scratch by DCD’s engineers. Since 1999 the company has released over 70 different architectures, among them is the DQ80251, world’s fastest 8051 CPU. – Of course, the D32PRO is an effect of our market experience – adds Krzyzak – but it’s a completely new, innovative solution. We are engineers, so we know the problems we all face in our work – why waste silicon, why limit performance, why shorten peripherals list? The D32PRO answers all these questions.

All peripherals on board

The D32PRO has been equipped with Floating Point Coprocessor and great variety of available peripherals like e.g. USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC, Smart Card etc. Other peripherals can be effortlessly added to the CPU by using standardized interfaces.

Variable pipeline – ultimate code density

The D32PRO is a universal & fully configurable solution, which effectively executes application codes with many jumps (e.g. switching decision tree) as well as homogeneous ones (e.g. arithmetic operations). This wouldn’t be possible without variable pipelining. Another innovation is brought in the command list, which is based on special instructions – derivatives to the higher level language like e.g. C. That approach enabled ultimate code density, which goes in hand with efficient and compact instructions set. Variable length instructions are based on 16 bits and can be executed conditionally. The D32PRO implements the best features of the embedded microcontrollers, where one of them enables efficient cooperation with the at-tached peripherals, thanks to dedicated bit instructions.
The D32PRO has been equipped with 13 general registers R0-R12 and most of them are being refreshed automatically after interruption. Thanks to it the CPU accelerates interrupts and context switching in real time systems. And if it’s still not enough, the D32PRO has been equipped with one non-maskable and dozens of real-time reconfigurable interrupts: like its activity, priority level and number of automatically stacked registers.

Low energy for (not only) IoT

The D32PRO emphasizes low energy consumption, which is crucial in modern electronics. This is achieved thanks to special PMU (Power Management Unit), which dynamically controls the clock’s frequency. Thanks to it an engineer can program energy-saving mode for the CPU, where all the peripherals will be working with nominal clock. Moreover, the CPU itself can be moved to STOP mode with the clock detached from it. Then it can return to normal mode by an interrupt from any peripheral. In order to save additional power, the CPU can easily switch off the peripherals which are unused at the current moment.

Debugger – Bootloader

The D32PRO, similarly to DCD’s 8051 IP Cores, is delivered with a built-in hardware debugger. But this special solution has been tailored for 32-bit CPU, that’s why it enables full control from Eclipse level (complete Eclipse debugging system with GCC => USB 2.0 cable => D32PRO). Moreover, in DCD’s debugger only two pins have been used as optimal tradeoff between communication throughput and consumed resources, when in competitive solutions communication needs at least 5 pins (JTAG). Hardware bootloader unit enables firmware memory updates directly from external low cost Flash memory connected through the (Q)SPI interface. Moreover, the bootloader is equipped with hardware encryption mechanism which significantly protects firmware against reverse engineering.
More information: www.dcd.pl

Technical information:

• D32PRO, deeply embedded, royalties-free 32bit CPU
• CoreMarks/MHz CoreMarks: 2.41
• Dhrystone 1.48 / 2.67 DMIPS/MHz
• Power consumption (90nm) under 7µW/MHz (90LP)
• Size (90nm) 10.6k/6.8k gates

DCAN-FD, CAN with Flexible Data Rate

DCAN FD, a Configurable CAN Bus Controller with Flexible Data-Rate targets autonomous cars & ADAS systems

 

Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has introduced the newest IP Core. The DCAN FD IP Core is a configurable CAN Bus controller with Flexible Data-Rate. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) in accordance to ISO 11898-1:2015. The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbps (even up to 8Mbps) and the payload (data field) is up to 64 byte long. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized.

Poland, Bytom, September the 26th, 2016. The DCAN FD is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. It conforms to Bosch CAN 2.0B specification (2.0B Active) and CAN FD (flexible data-rate) – in accordance to ISO 11898-1:2015.

Standard CAN requirements become insufficient in modern automotive. The carmakers demand more bandwidth and more throughputs for most CAN-based in-vehicle networks. The DCAN FD IP Core is also a good alternative for non-automotive projects where not the increasing speed is the target. The longer payload (more than 8 byte) becomes crucial then.

The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbps (even up to 8 Mbps) and the payload (data field) is up to 64 byte long. When only one node is transmitting, the bit-rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes need to be re-synchronized. – The core has a simple CPU interface (8/16/32 bit configurable data width), with small or big endian addressing scheme – explains Tomasz Krzyzak, VCEO in Digital Core Design. Hardware message filtering and 128 byte receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN FD is described at RTL level, allowing target use in FPGA or ASIC technologies.

Key features:

• Designed in accordance to ISO 11898-1:2015
• Supports CAN 2.0B and CAN FD frames
• Support up to 64 bytes data frames
• Flexible data-rates supported
• 8/16/32-bit CPU slave interface with small or big endianness
• Simple interface allows easy connection to CPU
• Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
• Data rate up to 8 Mbps
• Hardware message filtering (dual/single filter)
• 128 byte receive FIFO and transmit buffer
• Overload frame is generated on FIFO overflow
• Normal & Listen Only Mode
• Transceiver Delay Compensation up to three data bit long
• Single Shot transmission
• Ability to abort transmission
• Readable error counters
• Last Error Code
• Fully synthesizable
• Static synchronous design with positive edge clocking and synchronous reset
• No internal tri-states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus

Performance:

 

Deliverables:

• Source code:
  • VHDL Source Code or/and
  • VERILOG Source Code or/and
  • FPGA Netlist
• VHDL /VERILOG test bench environment
  • Active-HDL automatic simulation macros
  • NCSim automatic simulation macros
  • ModelSim automatic simulation macros
  • Tests with reference responses
• Technical documentation
  • Installation notes
  • HDL core specification
  • Datasheet
• Synthesis scripts
• Example application
• Technical support
  • IP Core implementation support
  • 3 months maintenance
    • Delivery of the IP Core and documentation up dates, minor and major versions changes
    • Phone & email support.

 

Information about Digital Core Design:

The company founded in 1999, since the beginning stands in the forefront of the IP Core market. High specialization and profound customer service enabled to introduce more than 70 different architectures. Among them is the world’s fastest 8051 IP Core, the DQ80251, which is more than 75 times faster than the standard solution. The same, D32PRO, which is a royalty-free and fully scalable 32-bit CPU creates new possibilities for modern projects. As an effect, over 300 hundred licensees have been sold to more than 500 companies worldwide. Among them are the biggest enterprises like e.g. Sony, Siemens, General Electric and Toyota. But a lot of DCD’s customers are small businesses, R&D laboratories or front/back end offices, which require exact solution tailored to their project needs. Rough estimations say that more than 500 000 000 devices around the globe have been based on Digital Core Design’s IP Cores.