DFSPI IP Core from DCD supports all serial memories available on the market.

CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL. It is called “CPU friendly” because it efficiently relieves it through configurable registers and… few additional innovations.

DCD’s CAN FD FULL IP Core is a versatile and adaptable solution for incorporating Controller Area Network (CAN) functionality into various systems. This IP module can be implemented independently, as a part of an ASIC, or FPGA. It adheres to the ISO11898-1:2015 standard, enabling seamless communication in accordance with popular industry protocols.

DCD’s CEO, Jacek Hanke, inquires about the rationale behind labeling it as “CPU friendly.” – This distinction can be attributed to its enhanced filtering capabilities, which effectively alleviate the strain on CPU resources. By swiftly directing crucial messages to the buffers, they are promptly received without delay. Conversely, less critical data, such as temperature instructions, are stored in a FIFO (First-In-First-Out) arrangement. Once the FIFO reaches its capacity, all the accumulated messages are then transmitted to the CPU.

This module provides support for both Classical CAN and CAN FD but to establish a physical connection to the CAN bus, external transceiver hardware is required. DCD’s solution utilizes a single or dual-ported Message RAM, which is located outside of the module itself. This storage medium is connected to the CAN FD Full through the Generic Master Interface, facilitating efficient message handling.

The Host CPU can easily connect to the CAN FULL IP Core module via the 32-bit Generic Interface, enabling seamless integration and streamlined data exchange. DCAN FD Full supports all popular wrappers available on the market like e.g.

• AMBA – APB / AHB / AXI Lite Bus
• Altera Avalon Bus
• Xilinx OPB Bus

The IP core is available in two versions – Basic and Safety-Enhanced.

The DCAN FD Full has been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and be provided together with detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step by step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.

The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD-SEMI delivers a complete FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.

This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD-SEMI may optionally deliver higher ASIL level ready IP. For further information and the optional features please contact our support.

More information: https://www.dcd.pl/product/can-fd-full/

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

DFSPI IP Core from DCD supports all serial memories available on the market.

Digital Core Design, the leading IP Core provider and System-on-Chip design house presents its latest DFSPI IP Core for access to NOR and NAND Flash Devices. And if universal NOR & NAND Flash IP is not enough… DCD’s DFSPI IP Core also supports MRAM, pSRAM, DRAM, and EEPROM – combining ease of use with reliability, low power, and speed under all conditions, including automotive, industrial, and other applications.

DFSPI IP Core is a real “combo” between all SPI IP Cores available on the market – it’s an SPI FLASH Controller with Execute in place – XIP (SINGLE, DUAL, QUAD, OCTAL SPI Bus Controller with DDR / DTR support and optional AES Encryption) + NOR & NAND Flash Memory Support for all serial memories available on the market.

– As an option, the DFSPI controller has built-in support for HyperBus^TM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification – explains Jacek Hanke, DCD CEO The same the SPI Controller allows easy communication with all available SPI FLASH memories.

The DFSP IP Core is compatible with the xSPI JESD251 standard, which can be accessed through a standard AXI4 slave interface. It offers backward compatibility with Octal SPI, QSPI, DSPI, and SPI interfaces. Furthermore, it supports the JEDEC SFDP Standard. The IP allows users to quickly access memory from the xSPI device in SPI mode. Alternatively, users can issue a command to switch to a different mode. Additionally, a DMA command can be used to copy memory from the xSPI device to any other location on the bus.

The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface with higher-performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, delivering it in the exact configuration that meets users’ requirements.

DCD SPI cores, are part of our growing peripheral family that also includes protocols such as I3C and IR. These cores have been successfully implemented in Embedded Microprocessor Boards, Consumer and Professional Audio/Video, Home and Automotive Radio, Low-power Mobile Applications, Communication Systems, and Digital Multimeters.

More information: https://www.dcd.pl/product/dfspi/

 

About Digital Core Design

DCD has been founded in 1999 and since the very beginning is focused on IP Core Innovations. During these 25 years company mastered more than 90 different architectures, which have been utilized in more than 750 000 000 electronic devices around the globe. Amin them one can find e.g. World’s Fastest 8051 CPU, World’s Tiniest 8051 IP Core, Royalty-Free and Fully Scalable 32-bit CPU, 100% safe cryptographic system and 32-bit plus 64-bit RISC-V CPUs. More information at dcd.pl

DCD will present our latest cryptographic and (not only) automotive solutions

Join us during the IP SoC Silicon Valley and RSA Conference in San Francisco. Mark the date: April 24th, 2023.

For our visitors, we’ve prepared some extras like e.g.

• 30% discount for all DCD’s cryptographic IP Cores
• two brand new RISC-V CPUs designed from scratch by DCD – and when 32-bit is not enough… maybe 64-bit will be an answer
•  enhanced CAN ecosystem (not only) for automotive – are you ready for CAN-XL?

Apart from the above our engineers will give you a sneak-peak into our latest and well-known solutions like e.g. CryptOne – 100% safe cryptographic system; CFD-SEMI – quantum leap for Computational Fluid Dynamics; EOL – Obsolete Parts Replacement; World’s Fastest 8051 CPU; Royalty-Free 32-bit CPU and more!

Join us in the… US 🙂

DCD will present new RISC-V, CAN, Cyber, and more during Embedded World

Join us during the Embedded World in Nurnberg, Germany. DCD’s Booth is located in hall 4 => 4-139a.

For our visitors, we’ve prepared some extras like e.g.

• free entry tickets 🙂 it’s not a joke – send as an e-mail at ew23@dcd.pl and get your ticket now
• two brand new RISC-V CPUs designed from scratch by DCD – and when 32-bit is not enough… maybe 64-bit will be an answer
•  enhanced CAN ecosystem (not only) for automotive – are you ready for CAN-XL?

Apart from the above our engineers will give you a sneak-peak into our latest and well-known solutions like e.g. CryptOne – 100% safe cryptographic system; CFD-SEMI – quantum leap for Computational Fluid Dynamics; EOL – Obsolete Parts Replacement; World’s Fastest 8051 CPU; Royalty-Free 32-bit CPU and more!

Join us: 14-16 March 2023, Booth 4-139a, Hall 4

Automotive is the key: DCAN

Digital Core Design, as a leading IP Core provider and System-on-Chip (SoC) design house, has been invited for a conference “Know-how transfer in automotive”. The conference was held during international Fair of Automation and Robotization in Industry at Expo Silesia, Poland.

Bytom, Poland November 17th, 2011. Digital Core Design as a proprietary automotive IP Core provider participated in fair show and the international conference devoted to know-how transfer. Poland and Silesia Region particularly is one of the leading country regarding to automotive business in Europe. Thanks to the main European FIAT fab and OPEL (General Motors) factory which manufacture their newest car models, growth rate is positive, even though economy crisis. Strict cooperation with concerns propels also proprietary solutions providers. – We noticed that safety & power safe technologies are becoming one of the most significant ones, not only in automotive – says Tomasz Krzyzak, vice-president at Digital Core Design – that’s why not only our CPU solutions but also “automotive” interfaces CAN or LIN are equipped with enhanced control and power safe solutions.
Like for example CAN is a keyword connecting the world of electronics with the world of automotive. Because of its fundamental role in all aspects of security and safety, trustworthy implementations are crucial. That’s why Digital Core Design developed unique IP Core, which delimits the highest quality standards. The DCAN is a standalone controller for the Controller Area Network (CAN), which is common used in automotive and industrial applications. What’s the most important, DCAN conforms to Bosch CAN 2.0B specification (2.0B Active). The Core has simple CPU interface (8/16/32 bit configurable data width), with little or big endian addressing scheme. The DCAN supports both standard (11 bit identifier) and extended (29 bit identifier) frames. Hardware message filtering and 64 byte receive FIFO enables back-to-back message reception with minimum CPU load. The DCAN is described at RTL level allowing target use in FPGA or ASIC technologies.

More information: http://dcd.pl/ipcore/131/dcan/

World’s fastest 80C51 CPU @ CeBIT

Digital Core Design invites cordially for CeBIT, digital industry’s biggest, most international event. At DCD’s stand B46, located in Hall 6, all the visitors will have a chance to see the world’s fastest 8051 CPU. There will also be a possibility to talk with DQ80251 designers, both at B46 stand and during the conference organized by Polish Ministry of Economy.

Digital Core Design, leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house from Poland has introduced the world’s most advanced 80C51 architecture. Thanks to the unique combination of instruction set and most of all optimized architecture, Polish company has achieved results which are more than 56 times better than standard 8051 and more than 70% more efficient, than the nearest competition. – We’re proud to present the world’s fastest 80C51 CPU at CeBIT – says Piotr Kandora, VCEO, Director of R&D in Digital Core Design – That event is a heart of the digital world, that’s why we wanted to present our CPU there, to gain reliable information from IT and ICT professionals.
Digital Core Design is located at stand B46 in Hall 6, at the Polish National Pavilion, hosted by Ministry of Economy. DQ80251, world’s fastest 80C51 CPU will be presented from March 6th, till March 10th. There will be also an unique occasion to talk with the designers of the most efficient microprocessor on the first and the second day of the show. On Thursday anyone can join official presentation of DQ80251 during ICT conference held by Ministry of Economy of the Republic of Poland.

Polish Prime Minister amazed by DCD’s IP Core

CeBIT in Hannover, one of the most significant ICT event, has ended last Saturday. Once again this year, more than seven million business talks were held at CeBIT, among them, Digital Core Design’s. Polish IP Core provider, exhibiting at Poland’s National Pavilion, presented its newest  IP solution – DQ80251, the world’s fastest 8051 CPU. One of the first  to see it, was the Polish Deputy Prime Minister and Minister of Economy, Mr. Waldemar Pawlak.

 

 

Minister of Economy officially opened the Polish National Pavilion at CeBIT, which, as an event, for over 26 years, has been the most important global meeting platform for the ICT industry. – Therefore next year, Poland has a chance to be a strategic partner in the organization of CeBIT 2013. A strong representation of Polish ICT companies at this year’s fair is a good sign – said in  Hanover Deputy Prime Minister Waldemar Pawlak.
In CeBIT participated more than 4200 exhibitors from 70 countries, including 73 Polish companies in the ICT sector. Among them Digital Core Design, with the world’s fastest 8051 IP Core.  The DQ80251, which is 56 times faster than the standard 8051 and more than 70% much more efficient than the nearest competition, has been presented as a demo version at the Polish Stand.  – Several licenses of DQ80251 have been implemented in our customer’s projects, but not everyone can see them – said Jacek Hanke, DCD’s CEO – that’s why we had prepared a demo version for CeBIT visitors, who could watch a Full HD movie displayed thanks to FPGA with DQ80251 inside.
More information about Polish National Booth at CeBIT is available on the Ministry of Economy official web page: http://www.mg.gov.pl/node/15606  and additional information and technical data regarding the DQ80251, is being presented here: http://dcd.pl/news/342/the-world-s-fastest-8051-cpu/.

BYT-ON, Polish graphene processor works 3 months without battery charging.

No matter how you call it – Prima Aprilis, April Fools’ Day, All Fools’ Day, Aprilscherz, Jour du poisson d’avril or Hunt the gowk Day – thank you for your sense of humor and thank you that you took our joke.
yours sincerely,
DCD Team

Digital Core Design, Polish design laboratories from Bytom have developed the world’s first processor made of graphene. BYT-ON – that’s the name of this breakthrough solution – contains an unique architecture, which allows to process all operations with speeds reaching up to 1/300 the speed of light. Furthermore, it features minimal power consumption, as little as 1 fA/MHz, so that the processor can work even for 3 months on a single battery charge.

Bytom, 1st of April 2012. Graphene is an allotrope of carbon, discovered in 2004, for which in 2010, two physicists were awarded the Nobel Prize. Use of graphene in BYT-ON processor means a breakthrough in electronics, since the traditional silicon structure has been replaced with polycyclic aromatic hydrocarbons, of which the material is built. – We have started our tests just before the end of 2011 and the results exceeded our expectations – notes Tomasz Ćwienk, the spokesman for Digital Core Design – We fitted our processor in one of the newest tablets available on the market and much to our surprise, it worked from January till end of March, without charging the battery.
These revolutionary results were possible due to the combination of the Digital Core Design’s proprietary architecture (which is the outcome of 12 years of company’s experience) and the graphene itself, which opens brand new possibilities for the electronic industry. The architecture implemented in the BYT-ON processor is called CISKoRISK 2nd generation – it allows running all operations with speeds reaching up to 1/300 the speed of light, while maintaining 90% lower power consumption. The project has only one drawback – the price of the BYT-ON processor. It is built of micromechanically constructed graphene crystallite, of the size of cross-sectional area of human hair and its price oscillates around 1000$ – We are in the final phase of negotiations with banks, so everyone can buy this processor with 100 installments with 0% interest. – finishes Ćwienk.

Happy Easter!

You, my friend, are one
great reason to celebrate
this Easter season.
Wishing you an Easter that’s
as special as can be.
Happy Easter!

 

Hole-in-one: Company and Product of the Year

Digital Core Design, IP Core provider from Poland has been awarded with two prizes during Economic Award Gala Night. Mayor of Bytom, where DCD operates since 1999, for the first time in history awarded with two prizes just one company. So the Digital Core Design has been awarded as Company of the Year and it’s DQ80251, world’s fastest 8051 IP Core as Product of the Year.

Economic Award, which is granted by Mayor, has been established to promote the best companies based in Bytom and products which are designed locally, but targeted globally. Prize winners were selected from three nominees in every category. – Though DCD’s product presence is global, we don’t forget what is important in local scale – says Jacek Hanke, CEO – we’re proud that our work is being appreciated not only in the USA, Taiwan or China, but also in our home town.
This year’s Economic Award competition was very hard, because of the high requirements to be satisfied by the nominees. The runners up must inter alia create and secure good working conditions for employees, act for the local community and their products must be valued by the customers.
That’s why Digital Core Design has been awarded not only in one category, but for the first time in history, got a second award for the Product of the Year. DQ80251, which is the world’s fastest 8051 IP Core is more than 50 times faster than the standard introduced by Intel company.  – Our IP Core, thanks to its unique features, is a perfect choice for all embedded applications demanding cost effective and best possible solutions – concludes Hanke.

More information at http://www.bytom.pl/pl/10/1334385007/4

D16950 UART – All in One with IRDA onboard

Though the name suggests that it is dedicated only for 950, it also offers full compatibility with the most popular industry standards: 450, 550, 650, 750 and of course 950. Moreover, DCD’s IP supports IRDA data format mode, which combined with unique multitasking makes this IP Core one of the most advanced and flexible UART core.

Some say that UART should be named as a holy grail of every microcontroller. So if the market needs faster, more efficient and sophisticated MCUs, the same story goes with UARTs.  Need for speed  forces advanced solutions, both in software and hardware data flow control. That’s why D16950 enables Fast Mode – when normally 16 samples per bit are being sampled, then in Fast just 4-15. The Core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip – says Jacek Hanke, CEO Digital Core Design – Nevertheless it’s also proprietary solution for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface, D16950 core implementation and verification are very simple, just by elimination a number of clock trees in complete system.
The D16950 UART is functionally identical to the OX16C950, and as was mentioned above – fully compatible with the most popular industry standards: 450, 550, 650 and 750. It allows serial trans-mission in two modes: UART mode and FIFO mode. In the second one internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes.
D16950 includes also a programmable baud rate generator, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic. Provisions are also included to use this n × clock to drive the receiver logic. DCD’s IP Core is also equipped with complete MODEM-control capability and processor-interrupt system. It is fully customizable – interrupts can be programmed in accordance to specific requirements, mini-mizing the computing required to handle the communications link.
As all DCD’s UART Cores, D16950 includes fully automated testbench with complete set of tests al-lowing easy package validation at each stage of SoC design flow.

More information at:  http://dcd.pl/ipcore/130/d16950/

Datasheet available here: http://dcd.pl/workspace/documentation/gen/d16950_ds.pdf

DCD among National Finalists for EBA & DQ80251 for the UKTI Award of Innovation

Digital Core Design has been nominated as a National Finalist for the 2012/2013 European Business Awards. Europe’s most recognized business competition has appreciated DCD’s world’s fastest 8051 processor – the DQ80251 – for the UKTI  Award of Innovation. UK Government department for Trade & Investment and European Business Award committee, engaged with thousands of businesses across Europe to select the DQ80251 as a reflection of DCD’s success.

Just to emphasize, Digital Core Design has been selected from several thousand companies across Europe for the UKTI Award for Innovation. Moreover DCD’s the only IP Core provider and design house qualified as a National Finalist. – We are absolutely overjoyed and proud to represent not only Poland, but also EDA/IP/SoC field  in the 2012/13 European Business Awards – says Jacek Hanke, CEO of Digital Core Design.
The EBA judging panel nominated the DCD’s DQ80251 for the UKTI Award of Innovation. One of the most advanced 8051 CPU presented in the beginning of 2012, is even 56 times faster than the standard invented by Intel company and more than 70% more efficient, than the nearest solution. What does it mean for the end-user? That it can perform more operations in shorter time and with less power consumption. Needless to say, the DQ80251 is the only virtual electronic component  nominee for the Innovation Award.
The European Business Awards, sponsored by RSM International, Infosys, Millicom International Cellular and supported by UKTI (UK Trade & Investment ), is an independent Awards programme, designed to recognize and promote excellence, best practice and innovation in the European business community, in line with broad aims of the European Union and business representative groups, across all European nations. José María Aznar, former Prime Minister of Spain, “I have the highest opinion of the European Business Awards. It is a great initiative to promote the values and principles we believe in: liberty, democracy, freedom of speech, open markets and open societies.”
The 2011 European Business Awards showcased organizations with a combined turnover of €1 trillion Euros (8.23% of EU GDP). These businesses employ over 2.7 million people across the continent.

More information about European Business Award:

http://www.businessawardseurope.com

D68000 IP Core with Linux, MAC & debugger

Digital Core Design, IP Core and SoC design laboratories from Poland have introduced the newest version of the Motorola’s 68000 16/32-bit microprocessor. D68000 is the industry’s low cost 32-bit MCU, offering not only a low cost entry point but also effective performance. Improved architec-ture enables this IP Core to run with uCLinux, so it can be  easily used as HTTP server or FTP client.

The D68000 is 100% compatible with original Motorola’s 68000 and as a proof, just to mention, that a test run on classic Amiga 500+ computer showed clearly that DCD’s CPU can be 1:1 replacement for original chip. But classic computers are not the target destination for the product, cause improved architecture, creates new possibilities. D68000 runs with uCLinux Operating System, which makes this IP Core interesting solution for embedded servers, certified to be used only with m68k processors. The BOA application is used as HTTP server and effective communication could be established through FTP protocol. uCLinux is a MMU‐less derivative of Linux Operating System adopted for embedded solutions. It provides all of the Linux benefits including superior stability, Common Linux Kernel API, multitasking, full featured TCP/IP networking, Virtual File System and reduces the amount of memory needed by its kernel and running applications [it utilizes just 400kB].
To make implementation process even easier DCD’s solution is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.  – We have built special testing platform to run D68000 with uCLinux Operating System – explains Jacek Hanke, President of Digital Core Design – And to make this IP Core more user friendly, it’s being equipped with DoCD-BDM hardware debugger.
New IP Core from DCD is a technology independent solution, which enables any engineer to imple-ment it in either Altera, Asic, Lattice or Xilinx technology. Of course D68000 is binary-compatible with m68k family of microprocessors, more over – DCD’s D68000 has a 16-bit data bus and a 24-bit address data bus. Its code is compatible with the MC68008, upward code compatible with the MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. The difference lies in improved instructions set, which allows to execute a program with a higher performance, than the standard 68000 core can offer. MULS, MULU take just 28 clock periods, the same as DIVS, DIVU. Optimized shifts and rotations, combined with shorter effective address calculation time and removed idle cycles make this IP Core much more power efficient.
To complement the D68000 offer, it’s being developed with DoCD-BDM hardware debugger, which provides debugging capability not only for the IP Core, but for the whole SoC system. DCD’s debug-ger is 100% compatible with BDM debug interfaces, working smoothly with its interfaces/cables: Public Domain cable, Macraigor Wiggler and P&E BDM cable. DoCD’s also fully supported by stand-ard debugging tools like GNU GD8 debugger, Cosmic ZAP debugger and Tasking debugger.

DMAC-RMII – the network functionality in design

DMAC-RMII is our newest hardware implementation of a media access control protocol, defined by the IEEE standard. The DMAC-RMII, in cooperation with an external PHY device, enables network functionality in design. This IP Core supports 10BASE-T and 100BASE-TX/FX IEEE 802.3-2002 compliant RMII PHYs.

The DMAC-RMII Core is able to work with the most popular processors available on the market, either 8., 16. and 32 bit data bus, with little or big endian byte order format. Moreover, it provides static configuration of PHY IC, conforming to the IEEE 802.3-2002 standard.  – We’ve always wanted to design the most “user friendly” solutions, that’s why our DMAC-RMII is also technology independent and thus can be implemented in variety of process technologies. – says Jacek Hanke, CEO, Digital Core Design.  As the Core has been developed for reuse in ASIC and FPGA projects, it’s been implemented in several commercial products already. The design is strictly synchronous with positive-edge clocking, no internal tri-states and with a synchronous reset.
When the configurability is just one part of the elusive puzzle, the compatibility issues become crucial. That’s why the DMAC-RMII IP Core supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant RMII PHYs. As it’s been stated above, Polish IP Core has a Reduced Media Independent Interface (RMII) for connection to external 10/100 Mbps PHY transceivers, which ensures maximum compatibility with a great variety of external CPUs or standard bus controllers. – As the host interface can be configured to work with 8., 16. or 32-bit data bus lengths with big or little endian order format – explains Hanke – the DMAC-RMII is compatible with most modern virtual component interfaces. In addition, AMBA, OCP, OPB and other optional standard interfaces are available, which makes the Core a flexible solution to be utilized in a variety of interface applications, including network devices (eg NICs-Network Interface Cards, routers, switching hubs etc.), embedded microprocessor boards, communication systems and other Systems On Chip (SoC) applications.

DoCD – DCD’s on Chip Debugger: powerful tool in the USB housing

DoCD is a complete debugging system, which consist of three main blocks:  Debug IP Core, Hardware Assisted Debugger (HAD2) and Debugging Software. V.6.01 offers real time, non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on chip software debugging. As an effect, prominently cuts debugging time.

Modern System-on-Chip designs are facing the problem of inaccessibility of important control and bus signals. They often lay behind the physical pins of the device and that is why traditional measurement instrumentation is useless in many cases. The best way to get around those limitations, is to use on-chip debug tools for the tasks verification and software debugging. – DoCD allows hardware breakpoints, trace, variables watch and multi C sources debugging – explains Jacek Hanke, DCD’s CEO – Moreover, our Debug Software can work both as a hardware debugger and a software simulator. Some tasks can be validated at software simulation level and after this step, you can continue real-time debugging, by uploading code into silicon.
Other advantage of an on-chip debugger, is its improved design productivity in an integrated envi-ronment, with graphical user’s interface. Thanks to it, DoCD offers ability to display/modify memo-ries’ content, processor’s and peripherals’ register windows, along with information tracing and abil-ity to see the related C/ASM source code. And as a final result, these are the key elements, that help to improve the design process and thereby, to increase productivity.
Complete DoCD system consists of three major parts:

• Hardware Assisted Debugger: Pendrive packaged – HAD2 is a small hardware adapter, that manages communication between the Debug IP Core (JTAG protocol) inside silicon and a USB port of the host PC, running DoCD Debug Software.
• Debug Software: is a Windows based application, compatible with all existing compilers and assemblers. The DS has been designed to work in two major modes: software simulator and hardware debugger mode. They allow pre-silicon software validation in simulation mode and then, real-time debugging of developed software inside silicon – using debugger mode. Once loaded, the program may be observed in Source Window, run at full-speed, single stepped by machine or C-level instructions or stopped at any of the breakpoints.
• Debug IP Core: is a real-time hardware debugger, which provides an access to all chip registers, memories and peripherals, connected to the IP Core. It controls CPU work, by non-intrusive method. The Debug IP Core is provided as VHDL or Verilog source code, as well as CPLD/FPGA EDIF netlist.

The DoCD provides a scaled solution – many SoC designs have both power and area limitations. Debug IP Core, can be scaled to control gate count. The benefit is fewer gates – for lower use of power and core size, while maintaining excellent debug abilities. Typically, all of the features are utilized in pre-silicon debug (i.e. hardware debugging or FPGA evaluation), with less features availed in the final silicon.

DCD with the title of Marka Slaskie

Digital Core Design, Polish IP Core provider and System-on-Chip Design house, was awarded in the 3rd edition of Marka Slaskie [Brand: Silesia] competition, organized by the Marshal of Voivodship and the Regional Chamber of Commerce. The company from Bytom has won in a prestigious “Product” category for designing the world’s fastest 8051 CPU – the DQ80251.

The gala summarizing the 3rd edition of Marka Śląskie [Marka Slaskie – Silesia Brand] competition took place on September 1st. The jury headed by Adam Matusiewicz, the Marshal of Silesia, awarded prizes in nine categories. This year’s laureate of the prestigious Marka Śląskie “Product” category is the DQ80251 processor, designed by Digital Core Design.  – I am glad, that our MCU has gained international, local and now regional recognition as well – said Jacek Hanke, the president of Digital Core Design, during the Saturday gala. DCD’s solution is also among Polish finalists in the European Business Awards competition and was recently awarded the Economic Prize by the Mayor of Bytom.

Digital Core Design company unveiled the DQ80251 – world’s fastest 8051 processor late last year. Thanks to innovative solutions, its performance is over 50 times higher than the standard originally developed by Intel. – Our processor performs more operations in less time and with lower power consumption – explains Hanke – which is the whole point of modern electronics.

DCD at Day of Science and Industry + 8th WTA General Assembly

In September Polish city of Gliwice will be the capital of the biggest “hi tech cities” from around the globe. It will welcome 40 representatives of the association, coming from all over the world; mainly from countries which today are the leaders in innovation – South Korea, Japan, Taiwan and China.

The General Assembly of the World Technopolis Association in fact constitutes three days of conferences, symposia and workshops along with a number of accompanying events, during which we will be able to meet people, who today create the history of the future. That’s way we’d like to invite you for the event – on 12th of September, you can visit us at Techno Park Gliwice, Booth No. 53, where our representatives will be demonstrating DCD’s latest IP Core solutions.
Go to: http://www.wta2012.com/ and get the details.

Vote for DCD’s DQ80251, the world’s fastest 8051 CPU

Digital Core Design has been nominated – as the only IP Core and SoC design house – for the European Business Award. Parallel to jury, everyone can vote for DCD in a public voting. Just go to the official web site:  link
and vote for the DQ80251, the world’s fastest 8051 CPU.

Since 2007, the European Business Awards has been recognized as one of the most significant competitions, which promotes success, innovation and ethics in the European business community. During the last few years, among EBA prizewinners, companies like Microsoft, Dell or FedEx have been awarded. Digital Core Design can become one of them, with the nomination for the world’s fastest 8051 CPU, the DQ80251. – We’re proud to be a representative for the whole electronic design community – says Jacek Hanke, DCD’s CEO.I’m sure that our latest CPU is a great example, demonstrating power of intellectual property in a large scale.
The public voting for European Business Awards is open till 17th of November, 5PM CET. It takes only few seconds to go to the  http://www.businessawardseurope.com/entries/detail/Poland/4683 and click “Vote”, next to DCD’s video.  The company which will gain the biggest number of public votes, will automatically become a National Champion, which is a gateway for the prestigious Ruban d’Honneur prize.
More information: link.

 

USB [IP Core] combo pack from DCD

Digital Core Design, an IP Core provider and System-on-Chip design house from Poland, has introduced a USB [IP Core] combo pack, which consists of Audio, Human Interface Device and Mass Storage platforms. It’s only up to the project criteria, if either a standalone USB Device Controller or a complete set of USB solutions will be implemented in silicon.

The Universal Serial Bus (USB) connects more than computers and peripherals. Some say, that it has the power to connect the whole new digital world. That’s why, a trusted and safe connection is crucial. – Nowadays it’s hard to imagine a digital device without a USB port – no matter if it’s a standard, mini, micro or even a converter – says Jacek Hanke, CEO of Digital Core Design – And for that reason, we introduced the USB [IP Core] combo pack, which is a complete solution for almost all Universal Serial Bus related designs.
The DUSB2 is a hardware implementation of a full/high-speed peripheral controller, which interfaces to the UTMI bus transceiver. It contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, as well as endpoints number recognition logic and endpoints FIFO control logic. DCD’s solution is designed to support 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates. Moreover, as the DUSB2 is technology independent, it can be implemented in a variety of process technologies. The core strictly conforms to the USB Specification (v2.0). It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
The USB 2.0 Mass Storage Design Platform is a complete, integrated solution, dedicated for a wide range of USB based Mass Storage Devices. Thanks to a compact code, it can be used in various applications, like portable flash memories, digital audio players, card readers, digital cameras and so on.
The second option, is a universal solution for a Human Interface Device Design Platform. A strict and fully synthesizable code allows implementation in a broad variety of target devices, inter alia keyboards, mice, tablets, steering wheels and gamepads. It can also be used in industrial devices, like e.g. barcode scanners or pen tablets.
And last but not least – the USB Audio Design Platform. With its distinguished marks, like a lite de-sign, small gate count and fast operation, DCD’s solution can be easily implemented in numerous audio projects, but it offers something more than just a standard solution for microphones or speakers.

More information: /ipcores/67/

DT8051 – the world’s most powerful tiny 8-bit CPU

Digital Core Design, IP Core provider and a System on Chip design house, has introduced the DT8051. The newest IP Core from Poland is the world’s most powerful tiny 8051 available on the market. The complete system with peripherals and the DoCDTM debugger needs just 6 650 ASIC gates, when a standalone CPU utilizes little else than 3k gates.

The DT8051 is an area optimized tiny soft core of a single chip 8-bit embedded microcontroller, based on the most popular 8051 MCU. The Polish IP Core seems to be an excellent solution, also regarding to 32-bit ARM Cores, when even a plain M0 utilize more than 10000 gates. – In terms of  the cost & area of silicon-proven DT8051, not just other 8-bit MCUs, but also a 32-bit processor licensing comes close – says Tomek Krzyzak, the Vice President of Digital Core Design. Moreover, our DT8051 can run in very small FPGA devices or can be just a tiny fragment of a System-on-Chip ASIC – as the old saying goes: small is beautiful. A very low gate count area allows as well to run the core at high performance, up to 300 MHz in Hynix 0.18 library (equivalent performance to the original 80C51, clocked with 2400 MHz).
The DT8051 soft core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller, but in comparison to its ancestor, DCD’s IP Core has a very low gate count architecture, giving 6 650 ASIC gates for the complete system with peripherals and the DoCDTM on-chip debugger. But the size wouldn’t mean anything, without an appropriate performance. – The DT8051 could be named a “mighty power” – says Piotr Kandora, a VP & Director of R&D at DCD. Dhrystone 2.1 benchmark program runs exactly 8.1 times faster, than the original 80C51 at the same frequency. So the performance results are more than 2 times higher than the nearest competitive designs.
The DT8051 includes a 2-wire DoCDTM on-chip debugger (TTAG), up to eight external interrupt sources, an advanced Power Management Unit, Timers 0&1, I/O bit addressable Ports, full duplex UART and interface for external SFR. Furthermore, DCD’s IP Core has a built-in support for the 2-wire TTAG interface – DCD Hardware Debug System, popular DoCDTM. This version of the debugger is dedicated for applications, where a number of external pins is limited.
The DT8051 is delivered with fully automated test bench and complete set of tests, allowing easy package validation, at each stage of SoC design flow.

DRPIC166X MCU, low-cost mixed with high performance

The good old fashioned PIC microcontrollers are finding their way into new applications like smartphones, gaming peripherals, audio devices and embedded solutions for eg innovative medical devices. Moreover, because the DRPIC166X has upward compatible architecture, it preserves investment in code development. And if it’s not enough, let’s just mention that DCD’s IP Core offers 1.3GHz virtual clock frequency and consumes just 37uW/MHz. 

The DRPIC166X is a low-cost high performance 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip), dual ported memory. To fulfill modern electronics requirements, our Core has been designed with a special concern about lowest possible power consumption. It consumes just 37 uW/MHz in 0.18u technology. But power consumption means nothing without reasonable performance. DRPIC166X is the pipelined Harvard RISC architecture, being 4 times faster, compared to original implementation. – PIC family is popular among many engineers due to low cost, wide availability, large user base and extensive collection of application notes – says Jacek Hanke, DCD’s CEO – that’s why we have not only reduced the power consumption, but also increased the performance, DRPIC166X offers 1.3 GHz virtual clock frequency in a 0.18u technological process (800 MHz virtual clock frequency in a 0.35u technology).
The DRPIC166X soft core is software-compatible with the industry standard PIC 16XXX microcontrollers. DCD’s IP Core implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses.
The same, it’s 4 times faster compared to the standard architecture. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage is that the instruction fetch and memory transfers can be overlapped, by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory – explains Hanke. Most instructions are executed within 1 system clock period, except the instructions which directly operate on PC (GOTO, CALL, RETURN) program counter. The pipeline is being cleared and subsequently refilled at additional one clock cycle.
The DRPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices, telecom processors or consumer electronics. Built-in power save mode, makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC166X is delivered with fully automated testbench, complete set of tests and DoCDTM on-chip hardware debugger,  allowing easy package validation, at each stage of SoC design flow.

More information about DRPIC166X: /ipcore/82/drpic166x/

More information about PIC DoCDTM: /page/155/pic-docd/

DQSPI – quad performance SPI

Serial Peripheral Interface – Master/Slave with not only single and dual but most of all quad SPI Bus support, is the newest IP Core introduced by Digital Core Design. The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. IP Core supports all 8, 16, 32 bit processors and has been designed to offer the fastest available operations for any serial memory.

The DQSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. The system can be configured as a master or a slave device with data rates as high as CLK/2, when other vendors’ solutions offer just CLK/8. This quad SPI has been designed to offer the fastest available operations for any serial memory. Moreover the DQSPI has been design to operate with every 8, 16 or 32 bit processor available on the market.
The DQSPI is a fully configurable SPI master/slave device, which allows user to configure polarity and phase of serial clock signal SCK. It lets the microcontroller to communicate with fast serial SPI memories and serial peripheral devices. Moreover, it’s capable of interprocessor communications in a multi‐master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the four serial data lines. – In the Single SPI mode data is simultaneously transmitted and received – says Jacek Hanke, CEO in Digital Core Design – in DUAL and QUAD SPI modes – data is shifted in or out on respectively two or four data lines at once.
Clock control logic allows a selection of clock polarity, phase and a choice of four fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects bit rates for the serial clock. The DQSPI automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS7O – SS0O) and address SPI slave device to exchange serially shifted data. Error‐detection logic is included to support interprocessor communications.
A write‐collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple‐master mode‐fault detector automatically disables DQSPI output drivers, if more than one SPI device simultaneously attempts to become bus master.
The DQSPI supports two DMA modes: single transfer and multi‐transfer. These modes allow DQSPI to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DQSPI is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements.

DLIN, Local Interconnect Network IP Core [not only] for automotive

The DLIN is the newest Local Interconnect Network IP Core developed by Digital Core Design. Our solution is fully compatible with the LIN 1.3, 2.1 and the newest version 2.2 Revision A, released by the LIN Consortium. The core is described at RTL level, empowering the target use in both, FPGA and ASIC tech nologies.

The DLIN, DCD’s IP Core for Local Interconnect Network, is an ideal solution most of all for automotive designs. As technologies and facilities implemented in a car grow every year, the need for a cheap serial network has arisen. That’s why LIN seems to be the most suitable solution to integrate intelligent sensor devices or actuators in today’s cars. Contrary to the CAN, it enables cost competitive serial communication, building the same an extended vehicle’s electrical network, which… will be used as CAN’s sub-network.  – Our DLIN controller supports transmission speed between 1 and 20kb/s – says Jacek Hanke, CEO in Digital Core Design – that allows to transmit and receive LIN messages compatible to LIN 1.3, LIN 2.1 and also the newest LIN 2.2 rev A.
Compared to the CAN, LIN is slower, but thanks to its simplicity, it is much more cost effective. That’s why the DLIN is ideal for communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. DCD’s IP Core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as a master or as a slave LIN node, depending on a working mode determined by the microprocessor/microcontroller. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). DCD’s IP Core includes also a programmable timer, which allows to detect timeout and synchronization error. The Core is described at RTL level, empowering the target use in FPGA and ASIC technologies.

More information & data sheet: /ipcore/132/dlin/
DLIN presentation:   http://youtu.be/H72w8laPW5k

DQ80251 at the CeBIT 2013 opening ceremony The DuART, tiny UART IP Core.

DμART, the newest IP Core mastered by Digital Core Design, is one of the tiniest UART IP Cores available on the market. Small is beautiful, that’s why DCD’s tiny works not only in UART mode, but also implements separate BAUD clock line, false start bit detection, status report and internal diagnostic capabilities.

The DμART is a soft core of a Universal Asynchronous Receiver/Transmitter (UART). It can perform both, serial-to-parallel conversion on data characters received from a peripheral device or a modem and parallel-to-serial conversion on data characters received from the CPU. The CPU itself can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions, like overrun or framing.
The DμART includes also a programmable baud rate generator – says Jacek Hanke, CEO at Digital Core Design –  which is capable of dividing the timing reference clock input by divisors of 1 to (216-1) and producing a 16 × clock, for driving the internal transmitter logic. Provisions are also included to use this 16 × clock, to drive the receiver logic. The newest UART Core from Digital Core Design has been also equipped with a processor-interrupt system. Thanks to it, the interrupts can be programmed according to the user’s requirements, minimizing the computing required to handle the communications link.
The DμART core is perfect for applications, where the UART and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. DCD’s solution is also suitable for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices as well.

More information & data sheet: http://dcd.pl/ipcore/690/duart/

DI2CMS, I2C Master – Slave Bus Interface from Digital Core Design

Digital Core Design, an IP Core and System on Chip design house from Poland, has intro-duced its newest I2C Bus Interface soft core. It is fully compatible with Philips v. 3.0 spec-ification, which means it can operate at Standard, Fast, Fast Plus and High Speed (up to 3,4 Mb/s). Moreover DI2CMS allows master, slave mode, arbitration and clock synchro-nization, support for multi-master systems, 7-bit and 10-bit addressing formats on the I2C bus and some other valuable features.

DI2CMS provides an interface between a microprocessor or microcontroller and an I2C bus. It can work as a master or a slave transmitter/receiver – depending on a working mode, determined by the MCU. DCD’s IP Core conforms to the latest I2C v. 3.0 specification, implementing useful features like:

• Master & Slave operation [support for all speeds: Standard, Fast, Fast Plus, High Speed]
• Arbitration and clock synchronization
• Support for multi-master systems
• Support for both 7-bit and 10-bit addressing formats
• User-defined timings [data setup, start setup, start hold and others]
• Simple interface with support for: AMBA – APB Bus, Altera – Avalon Bus, Xilinx – OPB Bus
• Interrupt generation and more…

The DI2CMS is technology independent, that’s why a VHDL or VERILOG design can be implemented in a variety of process technologies. – Basing on 14 years market experience, we’ve wanted to design I2C IP Core, which will offer maximal functionality – says Piotr Kandora, VCEO, Director of R&D in Digital Core Design – That’s why DI2CMS implements almost all available functions, so it can be completely customized in accordance to the customer’s needs.
Digital Core Design’s family of I2C IP Cores consists of: DI2CM, DI2CS, DI2CSB and mentioned above DI2CSM. Depending on the target application they can work as a master, slave, base or master/slave. DI2CM –I2C Bus controller Master – realizes master communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as the I2C master transmitter and the I2C Master receiver. DI2CS – I2C Bus controller Slave – realizes slave communication between a microprocessor/microcontroller and an I2C Bus. It allow operations as the I2C Slave receiver and the I2C Slave transmitter. And last but not least DI2CSB – I2C Bus controller Slave – base version – realizes communication between an I2C Bus and a passive devices, like LCD drivers, memories etc.

More information & data sheet: http://dcd.pl/ipcore/119/di2cms/

Enterprise Day for young students at Digital Core Design

Digital Core Design has been participating in the 10th “Enterprise Day”, which is a day devoted to pupils from high schools and students. This special event is organized every year to encourage young people in finding their way to business and professional career. The Enterprise Day has been held under the patronage of Bronislaw Komorowski, President of the Republic of Poland.

Digital Core Design, leading IP Core provider and System on Chip design house from Bytom, Poland –  appreciates any initiative, which can support a local community. That’s why the company has been transported with joy, that three students from 1st High School in Bytom will become a part of the DCD team, at least for one day – Young people are making final decisions, which will influence their live – says Jacek Hanke, CEO at Digital Core Design – this is why we want to help them with this important step, by presenting our company and our business model.
This year’s “Enterprise Day” is organized on April 17th. The 10th edition has gathered almost 10k institutions, which will welcome pupils and students from around 1k of schools and universities. The event has been held under the patronage of Bronislaw Komorowski, President of the Republic of Poland.

DP8051 – fast & configurable 8051 with Instruction Smart Trace

The DP8051 is the 5th consecutive uncover of the 8051 IP Cores in Digital Core Design’s portfolio. Like its kinsfolk, it’s described by simplicity, high efficiency and performance. But unlike the competitive designs, it runs Dhrystone 2.1 benchmark program 11.46 to 15.55 times faster, which means, that this Pipelined RISC architecture executes up to 300 million instructions per second.

The DP8051 is a high performance, speed optimized soft core of a single-chip 8-bit embedded controller, intended to operate with fast (typically on-chip) and slow (off-chip) memories. Broad set of additional features and peripherals let the engineer to tailor the core to the specific application and/or hardware requirements. Moreover, the core has been designed with a special concern about power to performance ratio  – This ratio is extended by an advanced power management PMU unit – explains Tomasz Krzyzak, VP, Member Board of Directors at Digital Core Design – also there’s a bunch of serviceable peripherals available e.g. 2-15 interrupt sources, 4 interrupt levels, 2 data pointers, USB device, Ethernet controller, up to 4 timer/counters, 2 UARTs, 4 I/O ports and more. Depending on the configuration, the designer can likewise choose from e.g. compare/capture, watchdog, master/slave I2C Bus controller, Quad SPI, fixed point coprocessor or a floating point coprocessor.
The Dhrystone 2.1 benchmark score for the DP8051 shows speed improvement from 11.46 to 15.55over Intel® 80C51 at the same frequency. The same C compiler was used for benchmarking the core vs. 80C51, with the same settings. This performance can be also utilized as a great advantage in low power applications, where the core can be clocked over ten times slower than the original implementation, without performance depletion.
The DP8051, like all other DCD’s 8051 IP Cores, has a built-in support for the DoCD Hardware Debugger, which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCD provides non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). The IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows to improve the size of the IST buffer and extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed and then presented to the user as an ASM code and related C lines.

More information about DP8051: www.dcd.pl/ipcore/34/dp8051/  & http://youtu.be/zSk-NfyK-5I
More details about DCD on Chip Debugger: /page/154/docd/

DCD at the Malopolska Technology Trends 2013 in Cracow

Digital Core Design has been invited to the conference Technology Trends in Cracow, Poland. The conference will be held on 23rd and 24th of May at the congress centre of the Museum of Polish Aviation. DCD’s CEO, Jacek Hanke will have a lecture on the topic “Discover Digital World with Digital Core Design”.

International Conference Malopolska Technology Trends is the main event of the year-long program called “Technology Foresight”, which has been run by Cracow’s Technology Park and Malopolska IT Park. Digital Core Design has been invited along with other well-known companies like IBM, CISCO and Microsoft. – At this year’s CeBIT we had an interesting meeting with representatives of CTP – explains Jacek Hanke, DCD’s CEO – and during that meeting CTP’s CEO invited our company to be one of the event’s key speakers. Digital Core Design will have its slot on the 1st day of the conference, May 23rd, starting at 12.30p.m.
Malopolska Technology Trends conference is organized by Cracow’s Technology Park and Technology Forecast Centre. These two institutions invited representatives from “both worlds” – IT companies and respected scientists. During these days, they’ll be presenting their projects aiming in innovative ICT solutions.

 

More information about Malopolska Technology Trends: http://sse.krakow.pl/pl/malopolska-technology-trends/program.html

D68HC11 – HC11 legacy with all peripherals on board

The D68HC11 is fully software compatible with Motorola’s HC11. DCD’s IP Core offers legacy architecture cycle compatible with original microcontrollers, like 68HC11E, 68HC11A, 68HC11D, 68HC11F1, MC68HC11K0 MC68HC(L)11K1, MC68HC(L)11K4, MC68HC11KS2, MC68HC711K4, MC68HC711KS2, MC68HC11KW1. The D68HC11 can be used as direct replacement, pin-to-pin compatible with the original HC11 MCU.

Based on IP Core architecture improvement experience since 1999, Digital Core Design has in-troduced two options for the well-known D68HC11:

1. Standard – with preconfigured MCU, where configuration is identical to the original HC11

2. Optimized – an individual configuration with extra peripherals and additional custom blocks, required by the
application [There’s no need to waste time and money for unused features and wasted silicon]

What does it mean in real life/real design?  DCD’s D68HC11 IP Core family is based on 3 major options: E, F, K – explains Jacek Hanke, CEO at Digital Core Design – they are devoted to the specific original MCU, but in contrast to it – every single one of them adds an extra value to the design, which means, it already has integrated on-chip major peripheral functions. There are asynchronous serial communication interface (SCI) and separate synchronous serial peripheral interface (SPI) included. The main 16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Moreover, there’s a self-monitoring, on-chip circuitry included, which protects D68HC11E against system errors. The Computer Operating Properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides non-maskable interrupt, if the illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP are available, to conserve additional power. These modes make the D68HC11 IP Cores especially attractive for automotive and battery-driven applications – adds Hanke.
The D68HC11 IP Core, can be also equipped with the ADC Controller. This allows to use an external ADC controller with standard ADC software. This extra design feature added in DCD’s design makes external ADC’s visible in the same way, as internal ADC’s in the original 68HC11E Microcontrollers.
And last but not least, to make the D68HC11 even more adjustable, it’s been equipped with a built-in, real-time, on-chip hardware debugger, allowing easy software debugging and validation. Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
DCD’s IP Core comprises also fully automated testbench with complete set of tests, allowing easy package validation at each stage of SoC design flow.

More information about D68HC11: /ipcores/59/  & http://www.youtube.com/watch?v=1dtE1jHBO54
More details about DCD on Chip Debugger: /page/156/d68xx-docd/

DCD among 4 of the most innovative companies in Poland

During the official Gala held on 5th of June, President of the Republic of Poland, Mr Bronislaw Komorowski awarded 11 nominated out of more than 100 applied companies. Digital Core Design has been nominated for the Economic Prize in the prestigious category of Innovation, for its DQ80251, world’s fastest 8051 CPU.

Digital Core Design, Polish IP Core provider and System-on-Chip design house has been nominated in the Innovation category for the Economic Prize of the President of the Republic of Poland. Along with DCD, there’d been three significant companies nominated: Polpharma (medicine & biotechnology), PKO BP (the biggest Polish bank) and Vigo Systems (infrared detectors from Mars rover Curiosity). The prize went to the first company, for developing active substances which cure osteoporosis.  – We are the only IT company nominated for this prize, which itself is significant – said Jacek Hanke, CEO at Digital Core Design – that’s why standing along with 3 other most innovative companies in Poland, chosen from more than 100 runners-up, is very important for us.
Economic Prize of the President of the Republic of Poland is often called Polish Nobel Prize. It is a distinction for companies, institutions and inventors, which have significant influence in modernization and development of Polish economy.

 

 

 

 

More information:

http://www.prezydent.pl/kancelaria/nagroda-gospodarcza-prezydenta-rp/informacje-biezace/art,18,prezydent-wreczy-w-srode-nagrode-gospodarcza.html

http://www.prezydent.pl/kancelaria/nagroda-gospodarcza-prezydenta-rp/informacje-biezace/art,20,powinnismy-zabiegac-o-konkurencyjnosc-naszej-gospodarki.html

Digital Core Design has been awarded as a Microentrepreneur of the year 2013 by Citi

Digital Core Design, IP Core provider and System-on-Chip design house from Poland, has been awarded as a Microentrepreneur of the Year 2013 in the audit organized by the Kronenberg Foundation and Citi Bank. The jury, which includes businessmen, entrepreneurs and politicians, has chosen DCD’s application among more than 255 other runners-up.  The award is a recognition for the most innovative companies, which include in their business strategy social responsibility and quality of products.

The ceremony, which has been held in New Connect hall of the Warsaw Stock Exchange on June the 20th, was a summary of audit, ran among distinguished Polish companies. After a strict audit made in the nominated companies, the jury gave the highest appreciation to the Digital Core Design nomination. – This award means a lot for our company – said Jacek Hanke, DCD’s CEO – firstly, because our company has been audited by independent specialists from Citi Bank and Kronenberg Foundation, secondly – because we had tough competition, like Airoptic or Robotics Inventions.
This year’s event has been the 9th edition of the Microentrepreneur of the Year award. The Kronenberg Foundation and Citi Bank informed that in 2013 there’s been the biggest number of applications – 256. – We’ve awarded the most innovative companies – said Grzegorz Wach from Kronenberg Foundation – but it was important for us to award their quality and social responsibility.

More information:

http://www.citibank.pl/poland/kronenberg/polish/6158.htm

DLCD, customizable LCD controller

Digital Core Design, IP Core and SoC design house from Poland, has introduced a proprie-tary LCD controller equipped with 24-bit RGB output and synchronization. Moreover, like all DCD’s cores, the DLCD is provided as a fully synthesizable RTL therefore can be implemented in both ASICs/SoCs and FPGAs.

Whereas LCD technology is the most popular in digital imaging, DCD’s controller works smoothly also with CRT displays. Pixel data has an 8-bit resolution and a 24-bit RGB output is generated using external LUT with defined color palette. – Our LCD core is controlled by the CPU, which enables usage of an external data memory to display data – explains Tomek Krzyzak, VCEO at Digital Core Design –so all the parameters are configurable through the CPU register interface.
The core itself was designed to be used with DCD’s DQ & DP80xxx series of MCUs, which means, that it can be easily bundled with e.g. DQ80251, the world’s fastest 8051 MCU, as long as the other 51s like the DQ8051, DP8051 or DP80390 IP Core. All parameters are configurable by CPU but there is also capa-bility for setting parameters by modification constants in a source file. There’s no need to waste silicon resources for unused features and constant settings. The display controller is perfect for MCU based applications, where static graphic data is displayed using LCD/TFT matrix or e.g. CRT monitor.
Like all DCD’s IP Cores, the DLCD is provided as a fully synthesizable RTL so can be implemented in both ASICs/SoCs and FPGAs.

More information:

/ipcore/133/dlcd/ 

Flat or large 80390 CPU?

Digital Core Deisgn, IP Core provider and System-on-Chip design house has introduced the DP80390 soft IP Core, which is 100% binary compatible with 8051 and 80390 instruction sets. It’s pipelined RISC architecture executes up to 200 million instructions per second and consumes just 8120 gates. Furthermore, the DP80390 is a technology independent IP Core, so it can be easily implemented in both ASIC and FPGA.

The DP80390 is a high performance, speed optimized soft core of a single-chip 8-bit embedded controller intended to operate with fast (typically on-chip) and slow (off-chip) memories. It supports up to 8 MB of linear code space and 16 MB of linear data space. – We’ve designed this IP Core with a special concern about performance to power consumption ratio – explains Piotr Kandora, R&D Director at Digital Core Design – and this ratio can be extended by an advanced power management unit (PMU).
As it’s been stated above, the DP80390 soft core is 100% binary compatible both with 80390 and 8051 instruction set. One can easily choose from two configurations:

• Von Neumann, with common program and external data bus
• Harvard, where internal data and program buses are separated.

The pipelined RISC architecture of the DP80390 executes 85 – 200 million instructions per second, running the Dhrystone 2.1 benchmark from 11.46 to 15.55 times faster than the original 80C51 at the same frequency.  – This performance can also be exploited in low power applications – adds Kandora – where the core can be clocked over ten times slower than the original implementation, without performance depletion.
The DP80390 is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow. Each of DCD’s 80390 Cores has built in support for the DCD’s Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip. And unlike other on-chip debuggers, the DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals.

More information about the DP80390 is available at /ipcore/110/dp80390/

More information about DCD’s hardware debugger for DP80390: /page/154/docd/

Digital Core Design Wins Stevie Award in 2013 International Business Awards

Digital Core Design has won kudos in the Oscars of the business world, being the only EDA company awarded.  IP Core and System on Chip design house was named the winner of a Bronze Stevie® Award in the Company of the Year – Computer Services category in The 10th Annual International Business Awards.

Digital Core Design has been awarded for the broad line of trusted and silicon proven IP Cores, implemented in more than 250 million electronic devices around the globe. Since 1999 DCD is offering silicon proven solutions, which gained large popularity for the ultimate price to performance ratio. Among them is eg the DQ80251, the world’s fastest 8051 processor: – It is really something huge for us, being awarded together with such companies like Subaru, Shell or Coca-Cola – says Jacek Hanke, DCD’s CEO – that’s why I’m even more happy that our company has been honored by International Business Awards judging panel.
The International Business Awards are the world’s premier business awards program devoted to all individuals and organizations worldwide – public and private, for-profit and non-profit, large and small. The 2013 IBAs received entries from more than 50 nations and territories. Nicknamed the Stevies for the Greek word for “crowned,” the awards will be presented to winners at a gala awards banquet at the W Hotel in Barcelona, Spain on 14 October.
More than 3,300 nominations from organizations of all sizes and in virtually every industry were submitted this year for consideration in a wide range of categories, including Most Innovative Company of the Year, Management Team of the Year, Best New Product or Service of the Year, Corporate Social Responsibility Program of the Year, and Executive of the Year, among others.
Stevie Award winners were selected by more than 250 executives worldwide who participated in the judging process this year. – The 2013 International Business Awards are noteworthy for featuring the best collection of entries we have ever received – said Michael Gallagher, president and founder of the Stevie Awards,  – The judges have been unanimous in their comments about the quality of achievements, and the expertise with which they were portrayed, in the nominations we received this year.
Winners list is available at: http://www.stevieawards.com/pubs/iba/awards/408_2913_24120.cfm

The D26C92 UART IP Core offers more

The D2692 is a Dual UART Core software compatible with the SC26C92, SCC2692 and SCN2681. But on the contrary to it, DCD’s IP Core offers additional features and deeper FIFOs, like 8 character receiver, 8 character transmit FIFOs, watch dog timer for each receiver, mode register 0, extended baud rate, programmable receiver and transmitter interrupts.

The D2692 Dual Universal Asynchronous Receiver/Transmitter is a communication device that provides two full-duplex asynchronous receiver/transmitter channels in just one single package. DCD’s IP Core interfaces directly with microprocessors and may be used in a polled or interrupt driven system, furthermore provides modem and DMA interface. The operating mode and data format of each channel can be programmed independently. – Additionally, each receiver and transmitter can select its operating speed – says Jacek Hanke, DCD’s CEO – as one of 27 fixed baud rates, a 16X clock derived from a programmable counter/timer, or an external 1X or 16X clock. The opportunity to program independently the operating speed of the receiver and transmitter, denotes the UART particularly attractive for dual-speed channel applications like eg clustered terminal systems.
Every receiver is being equipped with FIFO to minimize the potential of receiver over-run and to re-duce interrupt overhead in interrupt driven systems. Moreover, the D2692 UART IP Core ensures a flow control capability, to disable a remote DUART transmitter, when the receiver buffer is full. To make this design even more functional, there’ve been added multipurpose 7-bit input port and a multipurpose 8-bit output port. They can be used as general purpose I/O ports or can be assigned to specific functions (eg clock inputs or status/interrupt outputs) under program control.

Detailed information: http://dcd.pl/ipcore/785/d2692/

DSPI_FIFO – SPI master slave enhanced with detectors

The DSPI_FIFO is a fully configurable SPI master/slave device, which allows to configure polarity and phase of a serial clock signal SCK. DCD’s core enables microcontroller to communicate with serial peripheral de-vices, but also to communicate with an interprocessor in a multi-master system. It supports all the features of SPI and transmission/reception FIFOs, to significantly reduce the CPU time.

The DSPI_FIFO system is flexible enough, to interface directly with numerous standard product peripherals, even from several manufacturers. The system can be configured as a master or as a slave device, with data rates as high as CLK/4. The clock control logic allows to select clock polarity and choose two fundamentally different clocking protocols, to accommodate most available, synchronous serial peripheral devices. When the SPI is configured as a master, the software selects one of eight different bit rates for the serial clock. – A serial clock line (SCK) synchronizes shifting and sampling of the information on two independent serial data lines – explains Jacek Hanke, CEO at Digital Core Design – so the data is simultaneously transmitted and received.
The DSPI_FIFO automatically drives selected by the SSCR (Slave Select Control Register) slave outputs (SS7O – SS0O) and addresses the SPI slave device to exchange serially shifted data. Error-detection logic is included to support interprocessor communication.
A write collision detector indicates, when an attempt is made to write data to the serial shift register, while a transfer is in progress. A multiple-master mode-fault detector automatically disables DSPI output drivers, if more than one SPI device simultaneously attempts to become a bus master.
The DSPI_FIFO supports two DMA modes: single transfer and multi-transfer. These modes allow the DSPI_FIFO to interface to higher performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers.
DCD’s IP Core is technology independent and silicon proven design. It is fully customizable, which means it is delivered in the exact configuration of customer’s requirements. – There is no need to pay extra for not used features and wasted silicon – ends Hanke. The DSPI_FIFO includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Detailed information: http://dcd.pl/ipcore/125/dspi-fifo/

Programmable Interrupt Controller D8259 from Digital Core Design

Digital Core Design, IP Core provider and the System on Chip design house from Poland introduced in its offer the D8259. DCD’s Programmable Interrupt Controller is fully compatible with the 82C59A device. As all other cores design by Polish company, the D8259 is tech-nology independent, so it can be implemented both in ASIC and FPGA.

The D8259 is a soft Core of Programmable Interrupt Controller, which is fully compatible with the 82C59A device. DCD’s IP core can manage up to 8-vectored priority interrupts for the processor. – But that’s not all, cause you can also program it to cascade and gain up to 64 vectored interrupts  – adds Jacek Hanke, DCD’s CEO. And if it still seems to be not enough, one can always get more than 64 vectored interrupts, by programming the D8259 to the Poll Command Mode.
The D8259 Package includes fully automated testbench. Thanks to complete set of tests, one can easily validate the whole package at each stage of SoC design flow. Same as all other DCD’s IP Cores, this one’s got also a technology independent design, that can be implemented in a variety of process technologies.
The D8259 can operate in all 82C59A modes and it supports all 82C59A features:

• MCS80/85 and 8088/8086 processor modes
• Fully nested mode and special fully nested mode
• Special mask mode
• Buffered mode
• Pool command mode
• Cascade mode with master or slave selection
• Automatic end of interrupt mode
• Specific and non specific end of interrupt commands
• Automatic and Specific Rotation
• Edge and level triggered interrupt input modes
• Reading of interrupt request register (IIR) and in service register (ISR) through data bus.
• Writing and reading of interrupt mask register (IMR) through data bus

More information about D8259 IP Core: http://dcd.pl/ipcore/134/d8259/

DCD’s HDLC/SDLC controller aims telecommunication

Digital Core Design has introduced our latest soft IP Core, the DHDLC. It’s been designed to control HDLC/SDLC transmission frame and optimized for great variety of 8, 16 and 32-bit MCUs. Same as all other DCD’s IP Cores, the DHDLC is a technology independent design, therefore can be implemented in both, ASIC and FPGA.

The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, no matter if it’s 8-, 16- or 32-bit microcontroller. The greatest advantage of this IP Core is the possibility to save MCU time wasted for handling HDLC/SDLC features, like bit stuffing, address recognition and CRC computation. To enable even more productivity, the DHDLC has an implemented FIFO buffer, for both receiver and transmitter. – We’ve designed the DHDLC IP Core, because… our customers asked us to do it so many times – explains Jacek Hanke, DCD’s CEO. Configurable core parameters and adjustable CPU interface are a must be in this project.
The DHDLC IP Core is fully synchronous with one clock domain design. All parameters are configurable by CPU, but there is also an another option. One can set all the parameters by modification constants in a source file. Thanks to it, there’s no need to waste silicon resources for unused features and constant settings.

DHDLC’s Key Features:

• Two separate receiver and transmitter interfaces.
• Two separate, configurable FIFO buffers for receiver and transmitter
• Bit stuffing and unstuffing
• Address recognition for receiver and address insertion for transmitter
• Two or one byte address field
• RC-16 and CRC-32 computation and checking
• Collision detect
• Byte alignment error detection
• Programmable number of bits for idle detection
• NRZI coding support
• Shared flags, shared zeros support
• Pad fill with flags option
• Transmitter clock generation
• 8-bit, 16-bit, 32-bit CPU interface
• Interrupt output for handling control flags and FIFOs’ filling
• Configurable core parameters

More information about the DHDLC IP Core: http://dcd.pl/ipcore/670/dhdlc/

DSMART, IP Core for smart card reader applications

Digital Core Design, introduced our latest solution, the DSMART. Based on ISO 7816-3/EMV4.2 requirements, it implements the hardware support for both T0 character oriented protocol and T1 block oriented protocol. Ipso facto, the Core is an answer to growing demand for solutions supporting the IC chip systems, visible in the previous months.

The DSMART is a fast, versatile and cost-competitive IP Core intended for smart card reader applications. It’s been designed to combine highly reduced CPU utilization & low area consumption, and to be able to activate and deactivate cards, perform resets, handle ATR reception and many additional features. – Small size, mobility and easy interaction with computers or other automated systems, create an instant demand for smart card systems – says Jacek Hanke, DCD’s CEO – Immediate update of the stored data opens new markets for the smart card systems e.g. in healthcare (identification and patient authentication), banking (wireless payment), transportation (electronic ticketing) and many others.
The DSMART is a configurable IP Core, so it can be easily adjusted to the project’s needs. Among proprietary options one can find, there’s e.g. data transfer to and from the host system which can be interrupt-driven or executed through Direct Memory Access (DMA). The automatic convention detection and decoding mechanism ensure the exact result, no matter of the used convention. Elementary Time Unit (ETU) – time duration of one bit is decoded from the received ATR interface byte and generated automatically. The card clock divider provides non-gated clock with a wide range of possible frequencies.
DSMART IP Core implements also a special power down mode, in which the card clock is being hold in two possible states, depending on the card parameter. Error signaling and character repetition are automatic for the T0 protocol. The DSMART incorporates also an optional CRC/LRC hardware checkingand generation mechanism which gives the convention independent result. The received CRC/LRC is not stored in the FIFO, so it can be read in case of CRC/LRC error. And, last but not least, the newest DCD’s IP Core provides optional block length counter to secure the DMA block transfer and automatic CRC/LRC, subjoining with a manual affixing option.

More information: http://dcd.pl/ipcore/884/dsmart/

 

DSMART’s Key Features:

• Compatible with the ISO 7816-3: 2006 and EMV 4.1 standard
• Support for asynchronous Smart Cards
• Dual configurable length FIFO with two programmable thresholds
• Card detection input
• Software-configurable interrupts
• Automatic convention detection and decoding
• Programmable non-gated card clock generator
• Automatic ETU generator
• DMA support for transmit and receive
• Hardware CRC and LRC calculations
• Card power down mode with clock stop high and clock stop low possibility
• Special fast block mode for T1 protocol (optional)
• CRC/LRC hardware generation and checking
• Byte counter with automatic CRC/LRC affixing(optional)
• No inertial tri-state buffers
• Fully synchronous synthesizable design

EEPROM IP Core with configurable SPI parameters

Digital Core Design, IP Core and System on Chip design house from Poland introduced its latest solution – DEEPROM. It performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Moreover, DCD’s IP Core DEEPROM implements configurable SPI parameters like serial clock prescaler, SPI mode, CS hold/setup.

Digital Core Design, celebrating in 2014 its 15th anniversary introduced newest IP Core which targets DRAM designs. The DEEPROM performs communication and exchanges data between external serial EEPROM Memory and CPU’s RAM memory interface. Contents are accessible to the CPU in the same manner as a common SRAM memory, but require READY input to expand the time access. – Our proprietary core allows to map serial EEPROM in processor memory space and control it as the parallel memory – says Jacek Hanke, DCD’s CEO. The controller automatically sends all control instructions and read /write memory locations. As for the CPU, the EEPROM is being connected to it through the DEEPROM. Moreover, it’s visible and controlled as parallel SRAM with long access time. – DEEPROM’s big advantage is that the core has been designed to operate with popular 25XXX SPI Serial EEPROMs from Atmel, Microchip – adds Hanke.
When all other factors are sustained, memory controller is becoming crucial. That’s why DCD’s IP Core has been developed to ensure the most accurate data flow. It was designed in accordance with JEDEC specification and all the other industry standards, which summarized together make the DEEPROM very small, efficient, with no internal tri-state buffers and signals IP Core.

More information: http://dcd.pl/ipcore/146/deeprom/

Watch the DEEPROM presentation on You Tube: http://youtu.be/lHbSfQAerlM

DEEPROM’s Key Features:

• Standard memory interface with ready control
• Configurable SPI parameters
• Serial clock prescaler
• SPI mode
• CS hold/setup
• Updating bits in EEPROM status register
• Simple interface allows easy connection to microcontrollers
• Fully synthesizable, static design with no internal tri-states

Enterprise Day for young students at Digital Core Design 100 million instructions for (good old?) M68HC08

DCD’s DF6808 IP Core is binary-compatible with the industry standard Motorola 68HC08 8-bit microcontroller, but thanks to highly sophisticated on-chip peripheral capabilities, it performs 45-100 million instructions per second. FAST architecture implemented in DF6808 enable this mcu to run at least 3 times faster than the original solution.

Digital Core Design, celebrating its 15th anniversary in 2014, enhanced its portfolio with a new architecture. DF6808, even in standard configuration, offers integrated on-chip major peripheral functions. But, as the company’s CEO Jacek Hanke has stated, it’s just the beginning: “The DF6808 Microcontroller Core contains full-duplex UART- Asynchronous Serial Communication Interface (SCI) and the Synchronous Serial Peripheral Interface (SPI)”. To enable even more functionality in design,  the main 16-bit, free-running timer system, has two input capture lines and two output-compare lines.
The DF6808 has been equipped with proprietary safety functions, which efficiently hasten the design process. To protect against system errors, self-monitoring circuitry has been included on-chip. The Computer Operating Properly (COP) watchdog system, protects against software failures. And an illegal opcode detection circuit provides a non-maskable interrupt, once the illegal opcode occurs.
Two software-controlled power-saving modes – WAIT and STOP are available to conserve additional power. These modes make the DF6808 IP Core especially attractive for automotive and battery-driven applications.
The DF6808 is fully customizable, which means it’s been delivered in the exact configuration, to meet target design requirements. There is no need to pay extra for unused features and wasted silicon. DCD’s IP Core includes fully automated test bench with complete set of tests. They allow easy package validation at each stage of SoC design flow.
And last but not least, the DF6808 has a built-in support for DCD Hardware Debug System called DoCD. It’s a real-time hardware debugger which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCD enables non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of micro-controller, including all registers, SFRs, user defined peripherals, data and program memories.

 

More information: http://dcd.pl/ipcore/113/df6808/

 

DF6808’s Key Features:

•  FAST architecture – 3.2 times faster than the original implementation
•  Software compatible with 68HC08 industry standard
•  Configurable Harvard or Von Neumann architectures
•  11 times faster multiplication
•  64 bytes of System Function Registers space (SFRs)
•  Up to 64K bytes of Data Memory
•  Up to 64K bytes of Code Memory
•  De-multiplexed Address/Data Bus to allow easy memory connection
•  Two power saving modes: STOP, WAI
•  Ready pin allows Core to operate with slow program and data memories.
•  Fully synthesizable
•  No internal reset generator or gated clock
•  Positive edge clocking and no internal tri-states
•  Scan test ready
•  800 MHz of virtual clock frequency compared to original implementation

D[I2C]SB requires no programming

DCD’s DI2CSB IP Core is a two wire, bidirectional serial bus, which provides stable and efficient short distance data transmission between numerous devices. A very simple interface, composed with read, write and data signals, allows easy connection to target device. The DI2CSB is a technology independent design, that’s why it can be implemented in a variety of both ASIC and FPGA technologies.

Digital Core Design, celebrating our 15th anniversary in 2014, enhanced portfolio with a new architecture. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc., and an I2C bus. – It can work as a slave receiver or as a transmitter – says Piotr Kandora, DCD’s Member of the Board – depending on the working mode determined by the master device. A clever interface, composed with read, write and data signals, allows easy connection to target devices. The core does not require any programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. – The DI2CSB core incorporates all features required by the I2C specification – adds Kandora – that’s why it supports Standard, Fast, Fast Plus and High Speed transmission modes.
The DI2CSB can be easily customized in accordance to project’s needs. For instance, the DI2CSB can be found in embedded microprocessor boards, consumer and professional audio/video, home and automotive radio, low-power applications, communication systems, cost-effective reliable automotive systems etc.

 

More information: http://dcd.pl/ipcore/121/di2csb/ 

 

DI2CSB Key Features:

• Conforms to the latest I2C specification
• Slave operation
  + Slave transmitter
  + Slave receiver
• Supports 3 transmission speed modes
  + Standard (up to 100 kb/s)
  + Fast (up to 400 kb/s)
  + Fast Plus (up to 1 Mb/s)
  + High Speed (up to 3,4 Mb/s)
• Allows operation from a wide range of input clock frequencies
• Support for reads, writes, burst reads, burst writes, and repeated start
• 7-bit addressing
• No programming required
• Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready

D16950 – ask for more from UART

DCD, celebrating our 15th anniversary, has released the D16950, which is an IP Core of a Uni-versal Asynchronous Receiver/Transmitter (UART), functionally compatible to the OX16C950. It allows serial transmission in two modes: UART and FIFO. In the FIFO mode, internal FIFOs are activated, allowing 128 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes.

DCD’s UART IP Core performs a serial-to-parallel conversion on data characters received from a peripheral device or a MODEM. And for those who need more, the D16950 enables also parallel-to-serial conversion on data characters received from the CPU. The processor can read a complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). – The D16950 includes a programmable baud rate generator, which is capable to divide the timing reference clock input by divisors of 1 to (216-1) and produce a n × clock for driving the internal transmitter logic – explains Jacek Hanke, DCD’s CEO.  Provisions are also included to use this n × clock to drive the receiver logic.
The D16950 UART IP Core is equipped with a complete MODEM-control capability and a processor-interrupt system. – Interrupts can be programmed in accordance to your requirements, minimizing computing required to handle the communications link – adds Hanke. The D16950 core includes all other UARTs (16450, 16550, 16650 and 16750) features and additional functions. Saying this, one can mention the ICR registers, which give additional capabilities of UART work configuration. The data transmission may be synchronized by an external clock connected to the RI (for receiver and transmitter) or the DSR (only for receiver) pin. The NMR register enables a 9-bit mode transmission, with or without special character. Writing and reading from/to FIFO may be controlled by trigger level registers, with any value set from 1 to 127.
DCD’s IP Core implements also auto flow control feature, which can significantly reduce software overload and automatically increase the system efficiency, by controlling serial data flow through the RTS output and the CTS input signals.
The D16950 is perfect for applications, where the UART core and the microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. Nevertheless, it’s also a proprietary solution for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal inter-face, the D16950 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system.
DCD’s IP Core includes fully automated test bench with complete set of tests, allowing easy package validation at each stage of SoC design flow. The D16950 is also a technology independent design, that can be implemented in a variety of process technologies.

More information: http://dcd.pl/ipcore/130/d16950/

 

D16950 Key Features:

• Software compatible with 16450, 16550,16650,16750 and 16950 UARTs
• Configuration capability
• Separate configurable BAUD clock line
• Majority Voting Logic
• Two modes of operation: UART mode and FIFO mode
  + In the FIFO mode transmitter and receiver are each buffered with 128 byte FIFO to reduce the number of interrupts presented to the CPU
  + In UART mode receiver and transmitter are double buffered to eliminate the need for precise synchro-nization between the CPU and serial data
• Configurable FIFO size up to 512 levels
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, DCD)
• Programmable Hardware Flow Control through RTS and CTS
• Programmable Flow Control using DTR and DSR
• Programmable in-band Flow Control using XON/XOFF
• Programmable special characters detection
• Trigger levels for TX and RX FIFO
• Interrupts and automatic in-band and out-off-band flow control
• Fully programmable serial-interface characteristics:
  + 5-, 6-, 7-, 8- or 9-bit characters
  + Even, odd, or no-parity bit generation and detection
  + 1-, 1.5-, or 2-stop bit generation
  + Internal baud generator
• Detection of bad data in receiver FIFO
• Clock prescaler from 1 to 31,875
• Enhanced isochronous clock option
• 9- bit data mode
• Software reset
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  + Loop-back controls for communications link fault isolation
  + Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  + AMBA – APB Bus
  + Altera Avalon Bus
  + Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states

A rethought PIC IP Core – the DRPIC1655X

Digital Core Design, IP Core provider and System-on-Chip design house, celebrating in 2014 15th Anniversary, presents the DRPIC1655X IP Core, which is compatible with the industry standard PIC 16XXX, but…  ensures 4 times faster architecture and 1 system clock instruction execution time. Thanks to its price and software simplicity, engineers can minimize the software development costs and enable easy portability across low to high-end platform.

The DRPIC1655X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast, dual ported memory. It’s been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the PIC IP cores market. – Especially now, when we see more demand from IoT projects – explains Jacek Hanke, DCD’s CEO – efficient solutions like DRPIC1655X are the right answer, cause one can find them for less than $1 in 10K quantities. But of course FPGA netlist is also available.
The DRPIC1655X Microcontroller perfectly fits in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC1655X IP core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements enhanced Harvard architecture (separate instruction and data memories), with independent address and data buses. The 14 bit program memory and 8-bit dual port data memoryallow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that instruction fetch and memory transfers can be overlapped by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data, from the data memory.
The DRPIC1655X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions, which operate directly on PC (GOTO, CALL, RETURN) program counter. – This situation requires the pipeline to be cleared and subsequently refilled – adds Hanke – This operation takes additional one clock cycle.
Last but not least, the DRPIC165X is delivered with fully automated testbench, complete set of tests and DoCD on-chip hardware debugger,  which allow easy package validation, at each stage of SoC design flow.
Unlike other on-chip debuggers, DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

More information: http://dcd.pl/ipcore/81/drpic1655x/

 

CPU Key Features:

• Software compatible with PIC16C55X industry standard
• Pipelined Harvard RISC architecture
  o 4 times faster, compared to original implementation
• 35 instructions
• 14 bit wide instruction word
• Up to 32 kB of internal Data Memory
• Up to 64K Words of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code
• 800 MHz virtual clock frequency in a 0.35u technological process

Digital Core Design awarded as National Champion and Technology Icon

Digital Core Design, an IP Core provider and System-on-Chip design house, has been awarded as National Champion in 2014/2015 European Business Awards. In the same time DCD has been chosen as a Technology Icon to promote hi-tech in Silesia and Poland. Both distinctions – in regional and global scale are a crowning achievement for DCD celebrating in 2014 its 15th Anniversary.

European Business Awards is an independent programme supported by global audit company RSM International. EBA is designed to recognize and promote excellence, best practice and innovation in the European business. This year’s edition engaged with over 24,000 business from 33 European countries but only 709 companies from across Europe have been named as National Champions; going through to the second phase of the competition.
– We’re very proud to be selected to represent both Poland and EDA industry as a National Champion –said Jacek Hanke, DCD’s CEO – And now we are looking forward to the next round of the judging process where we can explain in more depth how we are achieving business success.
Jean Stephens, CEO of RSM International, said: – Every year this competition gets tougher and more competitive as more companies, of varied sizes and across all sectors, chose to compete in this prestigious competition. It will be exciting to watch as we move through to the next round.
The second achievement comes from Silesian Voivodeship, where the Marshal’s Office has chosen Digital Core Design as a Technology Icon. The information campaign with a budget of more than 1 million PLN will promote hi-tech companies in press, media, ATL and BTL – to convict residents that e.g. company which designed World’s fastest 8051 CPU is located round the corner. – We act global, but don’t forget what’s important locally – points Jacek Hanke from DCD – from 15 years perspective, our location, proves that power of intellectual property knows no borders.

More information about European Business Awards: http://www.businessawardseurope.com/

More information about Technology Icon campaign: http://slaskie.pl/strona_n.php?jezyk=pl&grupa=3&dzi=1409641123&id_menu=615

A movie promoting Technology Icon Campaign: https://www.youtube.com/watch?v=beAKr66z_CU

D68HC11K with applications notes, development board & tools

Digital Core Design, celebrating our 15th anniversary this year, has introduced the D68HC11K, which is a synthesizable soft IP Core Microcontroller, fully compatible with the Motorola MC68HC11K industry standard. It can be used as a direct replacement for the microcontrollers like: MC68HC11K0, MC68HC11K1, MC68HC11K4, MC68HC711K4, MC68HC11KS2 and MC68HC711KS2.

In a standard configuration, the core has an integrated on-chip major peripheral functions. An asynchronous serial communication interface (SCI) and a separate synchronous serial peripheral interface (SPI) are included. The main16-bit, free-running timer system, contains input capture and output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. – This and additional modes make the D68HC11K IP Core especially attractive for automotive and battery-driven applications – says Jacek Hanke, DCD’s CEO. Memory expansion unit (with six address extension lines) allows up to sixteen 32K byte banks of external memory to be addressed in either of two bank windows. The MEU extension of memory space can be up to 1MB. Self-monitoring, on-chip circuitry is included, to protect D68HC11K against system errors. To enable optimal functionality in design, DCD’s IP Core implements eg:

• The Computer Operating Properly (COP) watchdog system, which protects against software failures
• An illegal opcode detection circuit provides a non-maskable interrupt, if illegal opcode is detected.
• Two software-controlled power-saving modes – WAIT and STOP avail to conserve additional power.

The D68HC11K Microcontroller Core can be equipped with the ADC Controller, which allows the us-age of external ADC Controller with standard ADC software. This ADC Controller makes external ADC’s visible in exact the same way as internal ADC’s in original 68HC11K Microcontrollers.
DCD’s IP Core is fully customizable – it is delivered in the exact configuration, to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests, allowing easy package validation, at each stage of SoC design flow.
And last but not least, to allow easy software debugging and validation, the D68HC11K has a built-in support for DoCD – a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC).
Unlike other on-chip debuggers, the DoCD provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers and SFRs, including user defined peripherals, data and program memories.
More information: http://dcd.pl/ipcore/88/d68hc11k/

Instruction Smart Trace – smart & non-intrusive

Digital Core Design, celebrating its 15th anniversary on the IP Core market, enhanced its 8051 portfolio with the functionality of an Instruction Smart Trace. So, starting from the most popular DP8051, through the DP80390, to the world’s fastest DQ8051 – all of them, thanks to an IST, can efficiently reduce trace memory size and increase traced program history.

Instruction Smart Trace is an inherent part of the DoCD^TM Hardware Debugger, which provides debugging capability of System-on-Chip (SoC). Unlike other on-chip debuggers, the tool provides non-intrusive debugging of a running application and saves designer’s time, thanks to the hardware trace, called Instructions Smart Trace buffer (IST). The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows improving the size of the IST bufferand extend the trace history. – For example, by using 256 Bytes of trace memory, we can store 128 program branches and decode much more program history, since the executed program is composed of normal opcodes (mov, add, mul, anl, etc.) and branches – explains Tomek Krzyżak, VCEO of Digital Core Design. – Based on this information stored in IST hardware memory, our DoCD.exe and Keil driver decode executed program and display this information as an ASM code and C code in trace history – he adds.
The DoCD Instruction Smart Trace buffer is configurable up to 8192 levels and is completely transparent for the debugged application. Its functionality enables real-time capture of executed instructions. Thanks to it, the engineer can later read-back to track-down the history of executed code, by using the DoCD debug software. – Instruction Smart Trace captures instructions in a smart and non-intrusive way, which means, that it doesn’t capture addresses of all executed instructions, but only instructions related to the start of the tracing, conditional jumps and interrupts – adds Krzyzak.
As an example, the trace buffer is 2kB, which means that up to 1024 levels can be captured. So there’s no wonder then, that it gives much greater history than 1024 instructions executed by the CPU. In the typical application IST enables to execute over 10k instructions, depending on how many conditional jumps and interrupts have been executed by the CPU.
Instruction Smart Trace has also configurable start/stop triggers, so the engineer can easily set the condition at which instruction tracing starts, but also when it should stop. But this is still not all, because the trace buffer can be changed or disabled dynamically. The IST uses the end of SXDM memory space, that’s why it can share the trace memory with the debugged programs. And when the debugging is finished, it assigns the whole memory back to the application.

DF6811E – 4 times faster architecture for HC11

Digital Core Design, celebrating our 15th anniversary in 2014, introduced the DF6811E IP Core. It aims at IoT sensors and beacons, but thanks to its binary compatibility with the Motorola’s 68HC11, it can be implemented in barcode readers, hotel card key writers, robotics, and various embedded systems.

 

The DF6811E is a redefined 8-bit MCU IP Core, with highly sophisticated, on-chip peripheral capabilities. Even though it is binary-compatible with the industry standard Motorola 68HC11 8-bit microcontroller, DCD’s IP Core has an improved FAST architecture. Thanks to it, it is approximately 4 times faster when compared to the original implementation. In the standard configuration, the core has integrated on-chip, major peripheral functions in one of below configurations:
+ 68HC11A
+ 68HC11D
+ 68HC11E
The DF6811E implements two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods. – Our Core offers also enhanced security by implementing self-monitoring circuitry included on-chip and the Computer Operating Properly (COP) watchdog system to protect against software failures – explains Jacek Hanke, DCD’s CEO. An illegal opcode detection circuit, provides a non-maskable interrupt, if illegal opcode is detected. Two software-controlled power-saving modes – WAIT and STOP, are available to conserve additional power.
The DF6811E Microcontroller Core can be equipped with the ADC Controller, which allows using an external ADC Controller with standard ADC software. The ADC Controller makes external ADC’s visible as internal ADCs in original 68HC11E Microcontrollers. The DF6811E has built-in real time, on-chip hardware  debugger – DoCD^TM, which enable easy software debugging and validation.
The DF6811E is a silicon proven and fully customizable solution. DCD delivers it in the exact configu-ration, which allows the licensee to save his time and money (there’s no need to pay extra, for not used features and wasted silicon). The package includes also fully automated test bench with complete set of tests to validate it at each stage of SoC design flow.

Complete USB Human Interface Design Platform

Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, introduced the USB HID Design Platform. It is complete and integrated solution which targets almost all aspects of USB based Human Interface Devices. Apart from that, DCD’s solution enhances Internet of Things (IoT) projects thanks to its software stack optimized with ultra-low power DP8051 8.bit CPU.

 

Highlights:

• DUSB2 peripheral controller, designed to support 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates
• DP8051XP ultra high performance, speed optimized, fully customizable 8051 8-bit microcontroller with built-in DoCD^TM debug IP core
• Human Interface Devices software stack optimized for DP8051XP 8-bit CPU
• FPGA board with ready to use, preprogrammed example HID application
• HAD2 – DoCD^TM Hardware Assisted Debugger board
• DoCD^TM Debug Software
• DoCD^TM driver for Keil development software
• DoCD^TM driver for IAR development software

Digital Core Design’s USB HID Design Platform is a complete and integrated solution created to enhance USB based Human Interface Devices design experiences. Mouses, keyboards, tablets but also hundreds of other e-quipment is based on stable USB connection. So it’s not a secret that a true programmable embedded system-on-chip integrating configurable analog and digital peripheral functions, is one of the biggest challenges engineers ever faced. – Our Human Interface Devices Design Platform offers the highest level of testability, conformance and verification – explains Tomasz Krzyzak, DCD’s Vice President, Member of the Board of Directors. This specific SoC seems to be the leading combination of all crucial elements implemented in one IP Core.
The USB HID Design Platform supports UTMI Transceiver Macrocell Interface as well as low cost Full Speed Macrocells. It’s been stacked with the DP8051 DCD’s IP Core, which guarantees 100% software compatibleness with ’51 industry standard. The same engineers gets up to 256 bytes of internal (on chip) Data Memory, up to 64K bytes of internal (on chip) or external (off chip) Program Memory. Last but not least, along with up to 16M bytes of external (off chip) Data Memory, goes a programmable Program Memory Wait States for wide range of memories speed.

More information http://dcd.pl/ipcore/93/hid-platform/

DI2CM – 12 years a… master

Digital Core Design introduced soft IP Core, targeting I2C design needs. The DI2CM core provides an interface between a microprocessor or microcontroller and the I2C bus. It can work as a master transmitter or master receiver – depending on a working mode, determined by the microcontroller. This universal solution is available with various system interface wrappers like AMBA – APB Bus, Altera Avalon Bus, Xilinx OPB Bus.

Saying that the I2C is a two-wire, bidirectional serial bus, which provides simple and efficient method of short distance data transmission between many devices, is quite obvious. But still, reality shows that the I2C bus can be very confusing, and not only for the newcomers.
The DI2CM core provides an interface between a microprocessor or microcontroller and the I2C bus. It can work as a master transmitter or a master receiver. It only depends on a working mode, determined by the microprocessor or microcontroller. – The DI2CM core incorporates all features required by the latest I2C specification – explains Piotr Kandora, R&D Director at Digital Core Design – this includes clock synchronization, clock stretch, arbitration, multi-master systems and high-speed transmission mode. The DI2CM IP Core has also been equipped with built-in timer, which allows operation for a wide range of clk frequencies.
DCD’s latest solution is a technology independent design, that’s why like all other company’s IP Cores, it can be implemented in a variety of process technologies.

More information http://dcd.pl/ipcore/118/di2cm/

 

Key Features:

• Conforms to the latest I2C specification
• Master operation: Master transmitter, Master receiver
• Support for all transmission speeds
  + Standard (up to 100 kb/s)
  + Fast (up to 400 kb/s)
  + Fast Plus (up to 1 Mb/s)
  + High Speed (up to 3,4 Mb/s)
• Arbitration and clock synchronization
• Support for multi-master systems
• Support for both 7-bit and 10-bit addressing formats on the I2C bus
• Interrupt generation
• Build-in 8-bit timer for data transfers speed adjusting
• Host side interface dedicated for microprocessors/microcontrollers
• User-defined timing (data setup, start setup, start hold, etc.)
• Available system interface wrappers:
  + AMBA – APB Bus
  + Altera Avalon Bus
  + Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready

World’s Fastest 8051 IP Core from Digital Core Design is 29 times faster

DQ8051, an extremely-fast 8051 MCU Core, which boasts a Dhrystone 2.1 performance rating of 0.27292 DMIPS/MHz, which therefore enables a 29.01 times speed-up over the original 80C51 chip operating at the same frequency. But the speed is not all, that’s why the DQ8051’s dynamic power consumption can be as low as 1.2µW/MHz. The same, it rivals not only all other 8051-compatible cores but also low-power 32-bit processors.

The 8051, apart from the fact that it was first introduced more than 30 years ago, is believed to be one of the most popular, or even the most popular microcontroller core in history. Many engineers have a lot of expertise with this CPU and there’s a great amount of legacy code and 8051-based tool chains around. But comparison between 8051 from 1981 with e.g. the DQ8051 from 2015 is worth as much as the comparison between first gasoline engine and modern hybrid engines.
– Using our fifteen years of experience on the market, we’ve mastered a great portfolio of 8051 IP Cores – says Piotr Kandora, Vice President at Digital Core Design – if our DT8051 is the World’s smallest 8051, then the DQ8051 is the World’s fastest 8051 for sure. The nearest competition stopped at 26x, with the power consumption almost two times higher than DCD’s.

DCD’s DQ8051 Dhrystone score rates at 29.01x the original at the same frequency, with the size of 7.5k gates. The nearest solution consumes almost 12k gates and achieves not more than 26x speed improvement. But the speed or power consumption is not all – adds Kandora. That’s why the DQ8051 is available with USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces. The core is also equipped with DoCD^TM hardware debugger with unique Instruction Smart Trace technology. IST doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method not only saves time but also allows improving the size of the IST buffer and extending the trace history. Captured instructions are read back by DoCD-debug software, analyzed and then presented to the user as ASM code and related C lines.
The DQ8051 is delivered with fully automated testbench and complete set of tests, allowing easy package validation at each stage of SoC design flow. This MCU IP Core is technology independent, that’s why it can be used in both ASIC and FPGA technologies.

DQ8051’s movie & presentation: https://www.youtube.com/watch?v=TKVuxJXa7C0

More information: http://dcd.pl/ipcore/197/dq8051/

 

DQ80251 from Digital Core Design is the World’s Fastest 8051 CPU

The DQ80251 mastered by Digital Core Design runs more than 75 times faster than the original 8051 chip, being the same the highest performance MCS51 instruction set compatible IP Core currently available. This fully configurable 80251 Microcontroller Core executes  the MCS-51 and MCS-251 instruction sets and is delivered with great variety of integrated peripherals like USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC and Smart Card. The DQ80251 is available through a global net of DCD’s distributors.

Digital Core Design launched its first version of the DQ80251 in 2011, offering performance 66 times faster than the original 8051 chip. It took the competitors almost 4 years to achieve similar results, that’s why DCD accommodated customers’ expectations and introduced fully configurable 80251 microcontroller which executes MCS-51 and MCS-251 instruction sets 75.08 times faster than the original chip. – Our DQ80251 boasts a Dhrystone 2.1 perfor-mance rating of 0.70579 DMIPS/MHz, which therefore enables a 75.08 times speed-up over the original 80C51 chip operating at the same frequency – says Tomasz Krzyzak, vice president at Digital Core Design – But the speed is not all, that’s why the DQ8051’s dynamic power consumption is also ultimate low. The same, it rivals not only all other 8051-compatible cores but also low-power 32-bit processors.

The DQ80251 is royalty-free, cost-effective 8051 IP Core with ultimate code density and instruction intelligence. – Thanks to it, the DQ80251 runs more operations in less time and consumes less power – adds Krzyzak. DCD enhanced the Core’s functionality by implementing great variety of integrated peripherals like USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC and Smart Card. And to enable more complex SoCs design, the DQ80251 is equipped with built-in on-chip debugger (DoCD^TM). It is a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, internal and external program memories and all SFRs, including user defined peripherals. – Nowadays 8051 CPUs gain their place in high-demand products, thanks to plenty of horsepower and many advantages like low costs, energy and area – summarizes Krzyzak – We neither can forget that the DQ80251 is easy to integrate and program. That’s why DCD’s IP Core, thanks to robust feature set, advanced power-saving features and World’s fastest performance, seems to be an appropriate solution for more complex applications.

More information: http://dcd.pl/ipcore/198/dq80251/

DQ80251’s presentation: https://youtu.be/jaXQTAR9RKU

Hardware debugger for the world’s fastest 8051 & 80251

Digital Core Design, an IP Core provider and a System-on-Chip design house from Poland, has recently informed about its world’s fastest 8051 & 80251 CPUs. To enable engineers even better experience with these unique solution, the company introduced a non-intrusive hardware debugger for DQ8051 and DQ80251. The system is called DoCD^TM (DCD’s on-Chip Debugger) and consists of the Debug IP Core, Hardware Assisted Debugger and Debug Software. It features inter alia instruction smart trace buffer (configurable up to 8192 levels), hardware debugging, software simulation and verification.

DoCD^TM provides some serviceable features like a real-time and non-intrusive debug capability, enabling a pre-silicon validation and post-silicon, on-chip software debugging. It allows hardware breakpoints, trace, variables watch and multi C sources debugging. – The DoCD^TM Debug Software can work as a hardware debugger, as well as a software simulator – explains Tomasz Krzyzak, vice-president at Digital Core Design – some tasks can be validated at software simulation level and after this step, it can continue real-time debugging by uploading code into silicon.

The DoCD^TM user can choose favorite C compilers or assemblers for software development – it supports most of High Level Object files produced by C/ASM compiler tools:

• Extended OMF-51 produced by Keil compiler
• IAR EWB 8051 & 80390 workbench
• OMF-51 produced by Tasking compiler
• Standard OMF-51 produced by some 8051 compilers
• Extended OMF-251 produced by Keil compiler
• NOI format file produced by SDCC-51 compiler
• Intel HEX-51 format produced by each 8051 compiler
• Intel HEX-386 format produced by each 80390 & 80251 compiler
• BIN format produced by each 8051 & 80390 & 80251 compiler

System-on-Chip designs are facing a problem of inaccessibility of important control and bus signals, because they often lay behind the physical pins of the device – that makes traditional measurement instrumentation useless. The best way to get around those limitations is to use on-chip debug tools for the tasks verification and software debugging. Other advantage of on-chip debugger is its improved design productivity in an integrated environment, with graphical user’s interface. Ability to display/modify memories’ content, processor’s and peripherals’ register windows, along with information tracing and ability to see the related C/ASM source code, are the key elements, that help to improve the design process and thereby, to increase productivity.
The DoCD^TM Hardware Debugger provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD^TM provides non-intrusive debugging of a running application. It can also efficiently save designer’s time, thanks to hardware trace, called Instructions Smart Trace buffer (IST). The DoCD-IST captures instructions in a smart and non-intrusive way, so it doesn’t capture addresses of all executed instructions, but only these related to the start of tracing, conditional jumps and interrupts. This method does not only save time, but also allows improving size of the IST buffer and extend the trace history. Captured instructions are read back by the DoCD-debug software, analyzed and then presented to the user as an ASM code and related C lines.

– The reason for the development of the DoCDTM, was to provide our customers with the ability of easy system verification and software debugging, at no additional charges – adds Tomasz Krzyzak from DCD – Therefore, we have decided to add the complete debug system to each 8051/80251/80390 IP Core – for free.
Now DCD’s customers have the exceptional possibility, to obtain the complete solution for mak-ing their own 8051 & 80251 based SoC, with the ability of pre-silicon validation and post-silicon software debugging – in one place. It’s really unusual opportunity for the designer, to have the ability to get a high quality IP Core and unique on-chip debug tool, from the same supplier.

More information: http://dcd.pl/page/154/docd/ 

D32PRO & DCD @ EXPO Milano, Italy

Digital Core Design will present its latest D32PRO CPU during prestigious EXPO universal exposition, in the Italian city of Milan. DCD has been qualified as one of the most innovative Polish companies, which will present their products during ICT Week at EXPO (October 12-18). The D32PRO is a silicon-proven, royalty-free 32-bit CPU, fully scalable to the project needs.

EXPO is recognized as one of the most prestigious promotional events in the world. It is a great opportunity to show the most innovative potential to a wider audience. Digital Core Design has been selected by the Ministry of Administration and Digitization (MAC) to present the D32PRO in a form of an interactive stand in the Polish pavilion on October 12-18 during Polish ICT Week at EXPO Milano 2015.
“Polish ICT week is a great opportunity for Digital Core Design to present its IP Core portfolio. For more than 15 years our company has been developing innovating architectures – says Jacek Hanke, DCD’s CEO. Polish ICT week at EXPO will be a chance for our company to present our latest solution to the world – the D32PRO. It’s a 32-bit, royalty-free, deeply embedded CPU, introduced in mid-September during the conference held at the Ministry of Economy in Warsaw. We haven’t forgotten that our presentation should offer something more to visitors. That’s why along with the CPU, we’ll use a special 3D hologram device to present D32PRO’s functionality. And this is just the beginning…”.
The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.48 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz. The minimal usable D32PRO CPU starts from 10.6k / 6.8k gates when optimized for area. Dynamic power is 7 microwatts/MHz with a 90 nm process (DCD’s IP Cores are synthesizable and foundry independent). The D32PRO has been equipped with C compiler and integrated CPU configurator. This makes DCD’s CPU fully configurable, both for ultra-low energy and for power-user projects.

Technical information:

• D32PRO, deeply embedded, royalties-free 32bit CPU
• CoreMarks/MHz CoreMarks: 2.41
• Dhrystone 1.48 / 2.67 DMIPS/MHz
• Power consumption (90nm) under 7µW/MHz (90LP)
• Size (90nm) 10.6k/6.8k gates

More information: http://dcd.pl/ipcore/1135/d32pro-fully-scalable-and-royalty-free-32-bit/

D32PRO, FULLY SCALABLE & ROYALTY-FREE 32-BIT CPU FROM DCD

The D32PRO is a 32-bit, deeply embedded and royalty-free IP Core. This silicon proven solution, based on RISC architecture but mastered on DCD’s experience dated since 1999, boosts performance to 1.52 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz. The minimal usable D32PRO CPU starts from 10.6k/6.8k gates when optimized for area. Dynamic power is 7 microwatts/MHz with a 90 nm process (DCD’s IP Cores are synthesizable and foundry independent). The D32PRO has been equipped with C compiler and integrated CPU configurator. This makes DCD’s CPU fully configurable, both for ultra-low energy and for power-user projects.

The D32PRO is a deeply embedded, royalty-free 32-bit CPU. Drawing on its valuable experience – like the world’s fastest 8051 – Digital Core Design created completely new, RISC 32-bit CPU. This silicon proven CPU enables engineers to tailor it to their needs – The D32PRO is fully scalable, hence it can be easily adjusted to get the efficiency comparable to ARM Cortex M0-M3 – explains Tomek Krzyzak, DCD’s vice-president – but there’s no problem to run the Core with maximal performance to get up to 1.52 / 2.67 DMIPS/MHz and 2.41 CoreMarks/MHz.
The D32PRO has been designed from scratch by DCD’s engineers. Since 1999 the company has released over 70 different architectures, among them is the DQ80251, world’s fastest 8051 CPU. – Of course, the D32PRO is an effect of our market experience – adds Krzyzak – but it’s a completely new, innovative solution. We are engineers, so we know the problems we all face in our work – why waste silicon, why limit performance, why shorten peripherals list? The D32PRO answers all these questions.

All peripherals on board

The D32PRO has been equipped with Floating Point Coprocessor and great variety of available peripherals like e.g. USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC, Smart Card etc. Other peripherals can be effortlessly added to the CPU by using standardized interfaces.

Variable pipeline – ultimate code density

The D32PRO is a universal & fully configurable solution, which effectively executes application codes with many jumps (e.g. switching decision tree) as well as homogeneous ones (e.g. arithmetic operations). This wouldn’t be possible without variable pipelining. Another innovation is brought in the command list, which is based on special instructions – derivatives to the higher level language like e.g. C. That approach enabled ultimate code density, which goes in hand with efficient and compact instructions set. Variable length instructions are based on 16 bits and can be executed conditionally. The D32PRO implements the best features of the embedded microcontrollers, where one of them enables efficient cooperation with the at-tached peripherals, thanks to dedicated bit instructions.
The D32PRO has been equipped with 13 general registers R0-R12 and most of them are being refreshed automatically after interruption. Thanks to it the CPU accelerates interrupts and context switching in real time systems. And if it’s still not enough, the D32PRO has been equipped with one non-maskable and dozens of real-time reconfigurable interrupts: like its activity, priority level and number of automatically stacked registers.

Low energy for (not only) IoT

The D32PRO emphasizes low energy consumption, which is crucial in modern electronics. This is achieved thanks to special PMU (Power Management Unit), which dynamically controls the clock’s frequency. Thanks to it an engineer can program energy-saving mode for the CPU, where all the peripherals will be working with nominal clock. Moreover, the CPU itself can be moved to STOP mode with the clock detached from it. Then it can return to normal mode by an interrupt from any peripheral. In order to save additional power, the CPU can easily switch off the peripherals which are unused at the current moment.

Debugger – Bootloader

The D32PRO, similarly to DCD’s 8051 IP Cores, is delivered with a built-in hardware debugger. But this special solution has been tailored for 32-bit CPU, that’s why it enables full control from Eclipse level (complete Eclipse debugging system with GCC => USB 2.0 cable => D32PRO). Moreover, in DCD’s debugger only two pins have been used as optimal tradeoff between communication throughput and consumed resources, when in competitive solutions communication needs at least 5 pins (JTAG). Hardware bootloader unit enables firmware memory updates directly from external low cost Flash memory connected through the (Q)SPI interface. Moreover, the bootloader is equipped with hardware encryption mechanism which significantly protects firmware against reverse engineering.
More information: www.dcd.pl

Technical information:

• D32PRO, deeply embedded, royalties-free 32bit CPU
• CoreMarks/MHz CoreMarks: 2.41
• Dhrystone 1.52 / 2.67 DMIPS/MHz
• Power consumption (90nm) under 7µW/MHz (90LP)
• Size (90nm) 10.6k/6.8k gates

More information: http://dcd.pl/ipcore/1135/d32pro/

DUSB2-ULPI, AN USB 2.0 DEVICE CONTROLLER WITH ULPI INTERFACE

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. The DUSB2-ULPI contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.

The DUSB2-ULPI is a hardware implementation of a full/high-speed peripheral controller that interfaces to an ULPI bus transceiver. DCD’s IP Core contains a USB PID and address recognition logic, state machines to handle USB packets and transactions, endpoints number recognition logic and endpoints FIFO control logic.
– It supports 12 Mb/s “Full Speed” (FS) and 480 Mb/s “High Speed” (HS) serial data transmission rates – explains Tomek Krzyzak, VP of DCD – of course we know that some might ask why not USB 3.0? – but honestly speaking in 99.9% of embedded applications, USB 2.0 is more than enough.
The design is technology independent and thus can be implemented in a variety of process technologies. This core strictly conforms to the USB Specification v 2.0 and ULPI v2.0. It is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
DCD’s USB IP Core portfolio includes also: Audio Platform USB 2.0 – Audio Devices Design Platform, USB 2.0 HID Platform – USB 2.0 Human Interface Devices Design Platform, USB 2.0 MS Platform – USB 2.0 Mass Storage Devices Design Platform, USB 2.0 DUSB2 – USB 2.0 Device Controller USB 2.0 (UTMI interface).

 

Technical information:

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Software configurable EP0 control endpoint size 8-64 bytes
• Software configurable 15 IN/OUT endpoints:
• configurable number of endpoints
• configurable type of each endpoint: INTERRUPT, BULK or ISOCHRONOUS
• configurable direction of each endpoint
• configurable size of each endpoint: 8-1024 bytes
• Supports ULPI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• Simple interface allows easy connection to the 8-, 16-, 32-bit CPUs
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Scan test ready

More information: http://dcd.pl/ipcore/1250/dusb2-ulpi/

D32PRO, our 32-bit CPU named the Product of the Future

The D32PRO is a deeply embedded, fully scalable and royalty-free 32-bit RISC CPU. It’s been designed from the scratch by Digital Core Design, the company known for more than 70 other IP Cores, among them e.g. the World’s Fastest 8051 IP Core, the DQ80251. The newest DCD’s CPU features performance up to 1.52 / 2.67 DMIPS/MHz or 2.59 CoreMarks/MHz and small footprint starting at 10.6k/6.8k ASIC gates.

“Polish Product of the Future” (Polski Produkt Przyszłosci – PPP) competition has been organized annually since 1997. Since 2008, the competition and promotion of winners is co-financed by the European Union. The competition’s objective is to promote and disseminate information on achievements of innovative techniques and technologies which have the opportunity to be applied on Global market. The competition is intended for innovative enterprises, research and development units, scientific institutes, research centers and also for individual inventors from EU Member States.

The Award Gala was held on November the 30th in Warsaw, Poland, where DCD’s CEO, Mr Jacek Hanke received the award from the hands of Mrs Patrycja Klarecka, PAED’s CEO. – We’ve designed the D32PRO from the scratch, basing on our best experience both from our World’s Fastest 8051 and several other innovative IP Cores – said Jacek Hanke, CEO of Digital Core Design – the D32PRO is silicon proven, fully scalable and like all other DCD’s IP Cores – royalty-free.
DCD’s 32-bit CPU has been awarded by Polish Agency for Enterprise Development not only for the performance, small footprint (starting at 10.6k/6.8k ASIC gates) and very high clock frequency (up to 1 GHz in modern ASIC technologies) but most of all for flexible licensing methods. – Starting from 1999, all of our IP Cores are royalty-free – said Jacek Hanke – many of our customers emphasized the lack of royalty-free 32-bit IP Cores, so… we made a step further and offer D32PRO in a royalty-free model and flexible Fast Track License.

All peripherals on board

The D32PRO has been equipped with Floating Point Coprocessor and great variety of available peripherals like e.g. USB, Ethernet, I2C, SPI, UART, CAN, LIN, RTC, HDLC, Smart Card etc. There’s no problem to add other peripherals to the CPU.

3-stage pipeline – ultimate code density

The D32PRO is a universal & fully configurable solution, which effectively executes application codes both with many jumps (e.g. switch tree) and homogeneous one (e.g. arithmetic operations). This wouldn’t be possible without variable pipelining. Another innovation lies in the command list, which is based on special instructions – derivatives to the higher level language like e.g. C. That approach enabled ultimate code density, which goes in hand with short and compact command list. The D32PRO has been equipped with 13 general registers R0-R12 and most of them are being refreshed automatically after interruption. Thanks to it the CPU accelerates interrupts and context switching in the real time systems. And if it’s still not enough, the D32PRO has been equipped with 1 non-maskable and several real-time reconfigurable interrupts: like its activity, priority level and number of automatically stacked registers.

Low power for (not only) IoT

Modern 32-bit CPU should be designed with a special concern for power-performance ratio. That’s why the D32PRO emphasizes low power consumption. This wouldn’t be possible without special PMU (Power Management Unit), which dynamically controls the clock’s frequency. Thanks to it an engineer can program power-saving mode for the CPU, where all the peripherals will be working with nominal clock. Moreover, the CPU itself can be moved to the STOP mode, with the clock detached from it. Then it can return to the normal mode by an interrupt from any peripheral. There’s no problem for the CPU to switch off the peripherals which are unused at the moment, and the same save additional power.

Debugger – Bootloader

The D32PRO, similarly to DCD’s 8051 IP Cores, is delivered with a built-in hardware debugger. But this special solution has been tailored for 32-bit CPU, that’s why it enables full control from Eclipse level (complete Eclipse debugging system, GCC => USB 2.0 cable => D32PRO). Moreover, in DCD’s debugger only two pins have been used, when in competitive solutions communication requires the use of at least 5 pins (JTAG). The hardware bootloader unit enables firmware program memory saving directly from external Flash memory connected through an SPI interface. Moreover, the bootloader has been equipped with a hardware encryption tool stored in non-volatile memory. It can significantly protect firmware against reverse engineering.

D32PRO, fully scalable 32-bit CPU from DCD awarded as the most innovative

The D32PRO is a deeply embedded, fully scalableand royalty-free 32-bit RISC CPU. It’s been designed from the scratch by Digital Core Design, the company known for more than 70 other IP Cores, among them e.g. the World’s Fastest 8051 IP Core, the DQ80251. Awarded D32PRO CPU features performance up to 1.52 / 2.67 DMIPS/MHz or 2.59 CoreMarks/MHz and small footprint starting at 10.6k/6.8k ASIC gates.

The non-commercial “Teraz Polska” Competition has been held for the past twenty years, under the honorary patronage of President of the Republic of Poland, awarding a group of best products and services, which thanks to their quality, technology and functionality, stand out in the market and can be a model for others.
– The Award for D32PRO IP Core is a second succesive distinction given to our silicon-proven CPU –  emphasizes Jacek Hanke, DCD’s CEO – It’s a proof that both customers and other industry experts estimate innovative product as our CPU.  Taking the Chance I can just point that this product is a basis for our next product which will be a 100% safe cryptCPU, called the CryptOne.
To date the Competition Jury has granted nearly 500 awards, which have entitled recipients to use the ”Teraz Polska” (“Poland Now”) Emblem and to take advantage of the Foundation’s promotional program, which offers discounts on advertising in the media, an opportunity to participate in foreign fairs and exhibitions co-organized by the Foundation, or membership in an elite “Teraz Polska” club, bringing together previous Awardees of the Competition.