Digital Core Design

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DI2CM – 12 years a… masterMar 5th, 2015

Digital Core Design introduced soft IP Core, targeting I2C design needs. The DI2CM core provides an interface between a microprocessor or microcontroller and the I2C bus. It can work as a master transmitter or master receiver - depending on a working mode, determined by the microcontroller. This universal solution is available with various system interface wrappers like AMBA - APB Bus, Altera Avalon Bus, Xilinx OPB Bus.

Saying that the I2C is a two-wire, bidirectional serial bus, which provides simple and efficient method of short distance data transmission between many devices, is quite obvious. But still, reality shows that the I2C bus can be very confusing, and not only for the newcomers.
The DI2CM core provides an interface between a microprocessor or microcontroller and the I2C bus. It can work as a master transmitter or a master receiver. It only depends on a working mode, determined by the microprocessor or microcontroller. - The DI2CM core incorporates all features required by the latest I2C specification – explains Piotr Kandora, R&D Director at Digital Core Design – this includes clock synchronization, clock stretch, arbitration, multi-master systems and high-speed transmission mode. The DI2CM IP Core has also been equipped with built-in timer, which allows operation for a wide range of clk frequencies.
DCD’s latest solution is a technology independent design, that’s why like all other company’s IP Cores, it can be implemented in a variety of process technologies.

More information http://dcd.pl/ipcore/118/di2cm/

 

Key Features:

  • Conforms to the latest I2C specification
  • Master operation: Master transmitter, Master receiver
  • Support for all transmission speeds
    + Standard (up to 100 kb/s)
    + Fast (up to 400 kb/s)
    + Fast Plus (up to 1 Mb/s)
    + High Speed (up to 3,4 Mb/s)
  • Arbitration and clock synchronization
  • Support for multi-master systems
  • Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Interrupt generation
  • Build-in 8-bit timer for data transfers speed adjusting
  • Host side interface dedicated for microprocessors/microcontrollers
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Available system interface wrappers:
    + AMBA - APB Bus
    + Altera Avalon Bus
    + Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready