The DBLCD32 core is a fully configurableuniversal LCD/TFT display controller which supports a wide range of resolution and enables both, horizontal and vertical synchronization parameters setup. The display’s pixel clock can be generated by an internal pixel clock divider based on the bus clock or delivered to the core by a dedicated pin. Additionally, there is a possibility of using an externally generated pixel clock. Polarization of generated pixel clock, as well as synchronization signals, is configurable. The DBLCD32 has a DMA capable master interface, which can be used to access a frame buffer placed directly in a system memory. Embedded DMA controller has configurable FIFO to store pixels data which increases system throughput and performance. Transmission on the master interface is burst oriented and there is a possibility of defining the burst size limit. Data fetched by the DMA interface can be translated to 24-bits RGB signals, depending on the selected color mode. There are three standard color modes supported:

 – 24-bits True Color,
 – 16-bits(5-6-5) High Color
 – 8-bits index color mode

Additionally, 32-bit True Color is also supported, but the MSB byte of each four byte word is ignored. In case of the Indexed Color Mode, the DBLCD32 is equipped with pixel palette RAM which is used to translate each byte from the display buffer into a 24-bit RGB output. There are two different formats of color palettes available. The core supports a page flipping mechanism, enabling use of multiple buffering totally without the tearing effect. There is also a set of programmable interrupts available related to both display synchronization and DMA status signals. The core is capable to work on both little and big endian systems. To increase system performance and flexibility of usage, the DLBLCD32 can be configured in two possible optimization levels, to find a proper balance between a gate count and a critical path length.

Key features

  • 24-bit RGB interface,
  • Configurable display resolution,
  • Configurable horizontal sync length and blanking,
  • Configurable vertical sync length and blanking,
  • Configurable RGB signals polarization,
  • Configurable pixel clock polarization,
  • Internal pixel clock divider,
  • Different pixel clock modes,
  • DMA capable interface,
  • Configurable DMA FIFO,
  • Configurable burst size limit,
  • AHB bus interface(32-bit)
  • 24-bit True Color mode support,
  • 16-bit (5-6-5) High Color mode support,
  • 8-bit Indexed Color mode support,
  • 32-bit True Color mode support (one byte ignored),
  • Pixel palette RAM,
  • Page flipping support,
  • Programmable interrupts,
  • Big and little – endian support,
  • Two different optimization levels,
  • Fully synthesizable, synchronous design.

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