Audio Platform

USB 2.0 Audio Design Platform – Complete USB Audio IP Solution

The USB 2.0 Audio Design Platform from DCD-SEMI is a fully integrated solution for USB-based audio devices, including microphones, speakers, and other audio peripherals. It combines high-performance IP cores, software stacks, and FPGA reference designs to accelerate development and simplify integration.

Key Features:

• DUSB2 Peripheral Controller supporting 12 Mb/s Full-Speed (FS) and 480 Mb/s High-Speed (HS) USB 2.0 data rates.

• DP8051XP Ultra-High Performance MCU, fully customizable 8-bit 8051 microcontroller with built-in DoCD™ debug IP core.

• Audio Devices Software Stack optimized for DP8051XP CPU, ready for immediate deployment.

• FPGA Board with preprogrammed example application for USB stereo speakers.

• HAD2 – DoCD™ Hardware Assisted Debugger for easy system validation.

• DoCD™ Debug Software and drivers for Keil and IAR development environments.

Benefits for Engineers:

• Complete turnkey solution for USB audio device development.

• Accelerates integration of USB audio peripherals in FPGA or ASIC designs.

• Reduces design and verification time with preprogrammed examples and automated debug tools.

• Fully compliant with USB 2.0 specifications, supporting both FS and HS modes.

Ideal Applications:

• USB microphones and headsets

• USB stereo and multichannel speakers

• Embedded audio interfaces and sound modules

DCD’s USB 2.0 Audio Design Platform delivers a ready-to-use, validated solution for engineers designing USB audio devices, ensuring fast time-to-market and robust performance.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Full compliance with the USB 2.0 specification
• Full-speed 12 Mbps operation
• High-speed 480 Mbps operation
• Supports UTMI Transceiver Macrocell Interface
• Synchronous RAM interface for FIFOs
• Suspend and resume power management functions
• 100% software compatible with industry standard 8051
• Up to 256 bytes of internal (on-chip) Data Memory
• Up to 64K bytes of internal (on-chip) or external (off-chip) Program Memory
• Up to 16M bytes of external (off-chip) Data Memory
• User programmable Program Memory Wait States solution for wide range of memories speed
• User programmable External Data Memory Wait States solution for wide range of memories speed
• Allows operation from a wide range of CPU clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Lite design, small gate count and fast operation
• Scan test ready