CAN FD Full
The automotive IPs are developed as ISO26262-10 Safety Element out of Context (ISO26262 soft IP SEooC, ASIL-B ready design)
CAN FD FULL IP Core is a missing gap between CAN FD and CAN XL. It is called “CPU friendly” because it efficiently relieves it through configurable registers and… few additional innovations.
DCD’s CAN FD FULL IP Core is a versatile and adaptable solution for incorporating Controller Area Network (CAN) functionality into various systems. This IP module can be implemented independently, as part of an ASIC, or on an FPGA. It adheres to the ISO11898-1:2015 standard, enabling seamless communication in accordance with popular industry protocols.
This module provides support for both Classical CAN and CAN FD but to establish a physical connection to the CAN bus, external transceiver hardware is required. DCD’s solution utilizes a single or dual-ported Message RAM, which is located outside of the module itself. This storage medium is connected to the CAN FD Full through the Generic Master Interface, facilitating efficient message handling.
The host CPU can easily connect to the CAN FULL IP Core module via the 32-bit Generic Interface, enabling seamless integration and streamlined data exchange. The Core supports all popular interface wrappers like e.g.
- AMBA – APB / AHB / AXI Lite Bus
- Altera Avalon Bus
- Xilinx OPB Bus
The IP core is available in two versions – Basic and Safety-Enhanced.
This sophisticated solution’s been developed as ISO26262-10 Safety Element out of Context. It can optionally be improved by necessary safety mechanisms and provide detailed safety documentation: all ISO26262 soft IP SEooC required work products, which include complete Failure Modes Effects and Detection Analysis FMEDA analysis with step by step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis. All the safety-related work products were checked by a third-party, independent audit.
The conducted safety analysis depicts, that the safety metrics are fulfilled and both IPs reach the Automotive Safety Integrity Level ASIL-B (Single Point Fault Metric SPFM > 90%, Latent Fault Metric LFM > 60%). DCD delivers a complete FMEDA analysis with step-by-step instruction to help to integrate the IP into the customer’s system and to conduct the system-level safety analysis.
This ASIL-B ready design may easily be used in Automotive Safety Systems at the ASIL-B level, but DCD may optionally deliver higher ASIL level ready IP. For further information and the optional features please contact our support.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Designed in accordance with ISO 11898‐1:2015 specification
- Supports CAN and CAN FD frames
- Supports up to 64 bytes of data frame
- Flexible data rates supported
- AUTOSAR support
- SAE J1939 support
- Simple 8/16/32‐bit CPU slave interface
- Data rate up to 8Mbps
- Up to 128 Base ID filters
- Up to 64 Extended ID filters
- 2 Configurable receive FIFO
- Up to 64 dedicated Receive Buffers
- Overload frame is generated on FIFO overflow
- Up to 32 dedicated Transmit Buffers
- Configurable Transit Buffers to FIFO or QUEUE
- Configurable Transmit Event FIFO
- Normal, Listen Only and Loopback modes supported
- Transmitter Delay Compensation up to three data bits long
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Timestamp according to CiA 603 support
- Two configurable interrupt lines
- Two clock domains (CAN clock and CPU clock)
- Fully synthesizable
- Static synchronous design with positive edge clocking and synchronous reset
- No internal tri‐states
- Scan test ready
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