CAN FD Full

DCAN FD FULL — Advanced CAN FD IP Core Bridging the Gap Between CAN FD and CAN XL

The DCAN FD FULL IP Core is a flexible, high-performance CAN controller designed to fill the crucial technology gap between CAN FD and CAN XL. Engineered as a fully “CPU-friendly” solution, it offloads the host processor through configurable registers, streamlined architecture, and several innovative design enhancements—ideal for modern automotive and industrial communication systems.

Full CAN FD Support Compliant with ISO11898-1:2015

DCD-SEMI’s DCAN FD FULL IP Core adheres to the ISO11898-1:2015 standard, providing seamless interoperability with widely used CAN industry protocols. It supports both Classical CAN and CAN FD, ensuring high data throughput, backward compatibility, and robust performance in real-time, safety-critical environments.

Designed for maximum design freedom, the module can be integrated:

• As a standalone component

• As part of an ASIC or SoC

• On FPGA platforms

To interface with the physical CAN bus, the IP Core uses external transceiver hardware, allowing easy adaptation to diverse automotive and industrial system architectures.

Optimized Architecture for Efficient Message Handling

The DCAN FD FULL IP Core uses a single- or dual-ported Message RAM located outside the module and connected via a Generic Master Interface. This approach enables:

• Efficient message storage and retrieval

• Reduced CPU load

• Scalable memory configuration

• High-speed, low-latency data handling

The host CPU connects through a 32-bit Generic Interface, simplifying integration and ensuring fast, predictable communication between system components.

Available in Basic and Safety-Enhanced Versions

The DCAN FD FULL IP Core is offered in two variants:

• Basic version – optimized for general CAN FD implementations

• Safety-Enhanced version – developed as an ISO 26262-10 Safety Element out of Context (SEooC)

The Safety-Enhanced variant includes optional functional safety mechanisms and ships with comprehensive ISO 26262 documentation, including:

• Full FMEDA (Failure Modes, Effects, and Diagnostic Analysis)

• Step-by-step integration guidelines

• System-level safety analysis support

• Verified and validated work products audited by an independent third party

ASIL-B Ready Functional Safety — Extensible Toward ASIL-D

The completed safety analysis confirms that the DCAN FD FULL IP Core meets all ASIL-B functional safety requirements, achieving the following key metrics:

• SPFM > 90% (Single Point Fault Metric)

• LFM > 60% (Latent Fault Metric)

These results validate the suitability of the DCAN FD FULL for integration into automotive systems targeting ASIL-B safety goals.
Additionally, DCD-SEMI can provide enhanced variants tailored to support architectures requiring higher safety integrity levels — including ASIL-D — to meet specific OEM or Tier-1 requirements.

Why Choose DCD-SEMI’s DCAN FD FULL?

• Fully compliant with ISO11898-1:2015

• Supports Classical CAN and CAN FD

• Bridges the gap toward CAN XL architectures

• Optimized, CPU-friendly design

• Flexible ASIC/FPGA implementation

• ASIL-B / ASIL-D ready, with optional higher-level safety features

• Backed by complete safety documentation and expert engineering support

CAN FuSa white papers

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

To learn more about DCAN FD FULL or request optional safety features, contact our team at info@dcd-semi.com.

• Designed in accordance with ISO 11898‐1:2015 specification
• Supports CAN and CAN FD frames
• Supports up to 64 bytes of data frame
• Flexible data rates supported
• AUTOSAR support
• SAE J1939 support
• 32‐bit CPU slave interface
• Data rate up to 8Mbps
• Up to 128 Base ID filters
• Up to 64 Extended ID filters
• 2 Configurable receive FIFO
• Up to 64 dedicated Receive Buffers
• Overload frame is generated on FIFO overflow
• Up to 32 dedicated Transmit Buffers
• Configurable Transit Buffers to FIFO or QUEUE
• Configurable Transmit Event FIFO
• Normal, Listen Only and Loopback modes supported
• Transmitter Delay Compensation up to three data bits long
• Ability to abort transmission
• Readable error counters
• Last Error Code
• Timestamp according to CiA 603 support
• Two configurable interrupt lines
• Two clock domains (CAN clock and CPU clock)
• Fully synthesizable
• Static synchronous design with positive edge clocking and synchronous reset
• No internal tri‐states
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Lite Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus