D16450

D16450 bridge to APB, AHB, AXI bus, it is a soft core of the Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C450. It performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, but also parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Reported information status includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16450 includes a programmable baud rate generator which is capable of dividing the timing reference clock input by divisors of 1 to (2¹⁶-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive receiver logic. Our proprietary solution also has a complete MODEM control capability and processor-interrupt system. Interrupts can be programmed according to your requirements, minimizing the computing required to handle the communication link. A separate BAUD CLK line allows setting an exact transmission speed, while UART internal logic is clocked with CPU frequency. The core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Our solution is also dedicated to a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to the D16450 universal interface, both core implementation and verification are very simple. They can be simply done by eliminating a number of clock trees in the complete system. The D16450 includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Our trustworthy solution is a technology-independent design, which can be implemented in a variety of process technologies.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with 16450 UART
• Configuration capability
• Separate configurable BAUD clock line
• Majority Voting Logic
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
• Fully programmable serial-interface characteristics:
  • 5-, 6-, 7-, or 8-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1,5-, or 2-stop bit generation
  • Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states