D16550

D16550 bridge to APB, AHB, AXI bus, it is a soft Core of Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the TL16C550A. It allows serial transmission in two modes – UART and FIFO. In the FIFO mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both, receive and transmit directions. The D16550 performs serial-to-parallel conversion on data characters received from a peripheral device or MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Reported status information includes the type and condition of transfer operations performed by the UART, as well as any error conditions (parity, overrun, framing or break interrupt). The D16550 includes a programmable baud rate generator, which is capable of dividing a timing reference clock input by divisors of 1 to (2¹⁶-1) and producing a 16 × clock for driving internal transmitter logic. Provisions are also included to use this 16 × clock to drive receiver logic. Our softcore incorporates complete MODEM control capability and a processor-interrupt system. What’s more important, interrupts can be programmed to your requirements, minimizing the computing required to handle the communication link. A separate BAUD CLK line allows setting an exact transmission speed, while UART internal logic is clocked with CPU frequency. During the Synthesis process, configuration capability allows you to enable or disable Modem Control Logic and FIFOs, or change the FIFO’s size. So, in applications with area limitation and where the UART works only in the 16450 modes, disabling Modem Control and FIFOs allow to save about 50% of logic resources. Our trustworthy Core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip. We recommend it also for a standalone implementation, where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to a universal interface, the D16550 core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. The D16550 includes a fully automated test bench with a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Please remember that our softcore is a technology-independent design, so can be implemented in a variety of process technologies.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with 16450 and 16550 UARTs
• Configuration capability
• Separate configurable BAUD clock line
• Majority Voting Logic
• Supports RS232 and RS485 standards (optional)
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 16 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• Independent receiver clock input
• MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Fully programmable serial interface characteristics:
  • 5-, 6-, 7-, or 8-bit characters
  • Even, odd or no-parity bit generation and detection
  • 1-, 1 ½-, or 2-stop bit generation
  • Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states