D16752

D16752 bridge to APB, AHB, and AXI bus, it is a universal asynchronous receiver/transmitter (UART) with 64-byte FIFOs and automatic hardware/software flow control. It offers enhanced features, like a transmission control register (TCR) which stores received FIFO threshold levels in order to start/stop transmission during hardware and software flow control. With the FIFO RDY register, the software gets a status of TXRDY/RXRDY for all UART ports in one access. Onboard status registers provide you with error indications and operational status modem interface control. System interrupts may be tailored to meet your requirements. An internal loopback capability allows onboard diagnostics. The UART transmits data sent to it from a peripheral 8-bit bus on TX signal and receives characters on an RX signal. Characters can be programmed to be 5, 6, 7, or 8 bits. The UART has a 64-byte receive FIFO and transmits FIFO, which can be programmed to interrupt at different trigger levels. The UART generates its own desired baud rate based on a programmable divisor and its input clock. It can transmit even, odd, or no parity and 1, 1.5, or 2 stop bits. The receiver can detect break, idle or framing errors, FIFO overflow, and parity errors. On the other hand, the transmitter can detect a FIFO underflow. The UART also contains a software interface for modem control operations and has software flow control combined with hardware flow control capabilities. The D16752 is the software compatible with the TL16C752. It provides a few enhanced features, which are provided through a special enhanced feature register. The UART will perform serial-to-parallel conversion on data characters received from peripheral devices or modems, and parallel-to-parallel conversion on data characters transmitted by the processor. The complete status of each channel of the D16752 can be read by the CPU at any time during functional operation. Our efficient core can be placed in an alternate mode (FIFO mode), relieving the processor of excessive software overhead which is run by buffering received/transmitted characters. Both, the receiver and the transmitter FIFOs, can store up to 64 bytes (including three additional bits of error status per byte for the receiver FIFO) and have selectable or programmable trigger levels. Primary outputs RXRDY and TXRDY allow signaling of DMA transfers. The D16752 has a selectable hardware flow control and software flow control. The hardware flow control significantly reduces software overhead and increases system efficiency, by automatically controlling serial data flow using the RTS output and CTS input signals. The Software flow control automatically monitors data flow by using programmable Xon/Xoff characters. The UART includes a programmable baud rate generator that can divide the timing reference clock input by a divisor between 1 and (216–1). A separate BAUD CLK line allows setting an exact transmission speed while UART internal logic is clocked with the CPU frequency. The D16752 includes a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Our efficient Core is a technology-independent design that can be implemented in a variety of process technologies. Configuration capability allows you to enable or disable the Modem Control Logic and the FIFO’s Control Logic as well as change the FIFO size during the Synthesis process. So, in applications with area limitation and where the UART works only in a 16450 mode, disabling the Modem Control and FIFOs allow to save about 50% of logic resources. The Core is perfect for applications where the UART core and microcontroller are clocked by the same clock signal and implemented inside the same ASIC or FPGA chip. Nevertheless, our solution is designed for a standalone implementation where several UARTs are required to be implemented inside a single chip and driven by some off-chip devices. Thanks to the D16752, the CPU interface core implementation and verification are very simple, just by eliminating a number of clock trees in the complete system. The D16752 can operate as a dual channel, as well as a single channel UART.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with 16752 UARTs
• Configuration capability
• Dual channel UART – configurable
• Separate configurable BAUD clock line
• Supports RS232 and RS485 standards
• Hardware/Software Data flow control
  • Programmable Xon/Xoff characters
  • Programmable AutoRTS, AutoCTS
• Programmable and selectable Transmit and Receive FIFO Trigger levels for DMA and interrupt generation
• Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
• Software Flow Control Turned OFF, optionally by any Xon Rx Character
• Software Selectable Baud Rate Generator Prescaleable Clock Rates of 1x and 4x
• Programmable SLEEP Mode
• Majority Voting Logic
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 64 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Configurable FIFO size allowing up to 512 levelsdeep FIFOs in both Rx and Tx directions.
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
• Fully programmable serial interface characteristics:
  • 5-, 6-, 7- or 8-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1.5-, or 2-stop bit generation
  • Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states