D16752

D16752 UART IP Core – TL16C752-Compatible Dual-Channel UART

The D16752 UART IP Core from DCD-SEMI is a highly configurable Universal Asynchronous Receiver/Transmitter (UART) designed for FPGA and ASIC integration. Delivered as a bridge to APB, AHB, and AXI bus architectures, it is software compatible with the TL16C752, making it ideal for legacy UART replacement, dual-channel communication, and embedded high-efficiency designs.

Dual-Channel Operation with 64-Byte FIFOs

The D16752 supports dual-channel UART operation with 64-byte receive and transmit FIFOs per channel, including 3 bits of error status per byte in the receiver FIFO.

• Programmable FIFO trigger levels

• FIFO RDY register provides TXRDY/RXRDY status for all UART ports in a single access

• Alternate FIFO mode reduces CPU overhead and enables efficient DMA transfers

These features make it a perfect solution for high-performance, low-latency serial communication.

Enhanced Hardware and Software Flow Control

The D16752 includes selectable hardware flow control (RTS/CTS) and software flow control (programmable Xon/Xoff characters).

• Hardware flow control automatically regulates serial data flow, significantly reducing CPU load

• Software flow control ensures smooth communication in complex multi-UART systems

• Transmission Control Register (TCR) manages FIFO threshold levels to start/stop transmission efficiently

Complete Status Reporting and Error Detection

The core provides full status visibility for each channel, including:

• FIFO conditions and trigger status

• Parity, framing, break, idle, and overflow errors

• Modem interface operational status

This ensures deterministic communication and simplifies firmware integration.

Programmable Baud Rate and Flexible Clocking

The D16752 features a programmable baud rate generator, capable of dividing a reference clock by 1 to (2¹⁶ − 1), and generating a precise 16× clock for transmitter and receiver logic.

• Separate BAUD CLK input allows exact transmission speed

• UART logic operates at CPU clock frequency

• Supports 5, 6, 7, or 8-bit characters, even/odd/no parity, and 1, 1.5, or 2 stop bits

Configurable Architecture for Area Optimization

During synthesis, designers can:

• Enable/disable Modem Control Logic

• Enable/disable FIFO Control Logic

• Adjust FIFO size

Disabling unused features in area-constrained designs can save up to 50% of logic resources, making it compatible with 16450 mode operation.

Ideal for SoC and Standalone Designs

The D16752 is suitable for:

• Shared clock domains inside FPGA or ASIC

• Standalone multi-UART implementations with several UARTs in one chip

Its universal CPU interface simplifies implementation and verification by reducing clock tree complexity.

Verification-Ready and Technology Independent

Like all DCD-SEMI UART IP Cores, the D16752 includes a fully automated testbench and a complete set of validation tests, ensuring smooth SoC integration.

It is technology-independent and can be implemented across a wide range of FPGA and ASIC process technologies.

Typical Applications

• TL16C752 / dual-channel UART replacement

• High-performance embedded SoCs

• Industrial automation and instrumentation

• Multi-UART FPGA designs

• Communication-intensive applications requiring flow control

UART IP Core Family Comparison

The table below compares DCD-SEMI UART and serial communication IP Cores to help FPGA and ASIC design engineers quickly select the optimal solution for their project requirements.

Selection Guidelines

• Choose D16450 for exact legacy 16450 / TL16C450 replacement.
• Choose D16550 when FIFO buffering and moderate CPU optimization are required.
• Choose D16750 for high-performance legacy replacement with deep FIFO and low CPU load.
• Choose D16752 for dual-channel high-performance UART with hardware/software flow control and 64-byte FIFOs.
• Choose D16950 for high-throughput UART with deep FIFO, synchronous mode, and advanced flow control.
• Choose D8530 when dual-channel USART and legacy protocol support are required.
• Choose DMESCC for advanced multiprotocol serial communication and block handling.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with 16752 UARTs
• Configuration capability
• Dual channel UART – configurable
• Separate configurable BAUD clock line
• Supports RS232 and RS485 standards
• Hardware/Software Data flow control
  • Programmable Xon/Xoff characters
  • Programmable AutoRTS, AutoCTS
• Programmable and selectable Transmit and Receive FIFO Trigger levels for DMA and interrupt generation
• Programmable Receive FIFO Trigger Levels for Software/Hardware Flow Control
• Software Flow Control Turned OFF, optionally by any Xon Rx Character
• Software Selectable Baud Rate Generator Prescaleable Clock Rates of 1x and 4x
• Programmable SLEEP Mode
• Majority Voting Logic
• Two modes of operation: UART mode and FIFO mode
  • In the FIFO mode transmitter and receiver are each buffered with 64 byte FIFO to reduce the number of interrupts presented to the CPU
  • In UART mode receiver and transmitter are double buffered to eliminate a need for precise synchronization between the CPU and serial data
• Configurable FIFO size allowing up to 512 levelsdeep FIFOs in both Rx and Tx directions.
• Adds or deletes standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• False start bit detection
• 16 bit programmable baud generator
• MODEM control functions (CTS, RTS, DSR, DTR, RI and DCD)
• Fully programmable serial interface characteristics:
  • 5-, 6-, 7- or 8-bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1-, 1.5-, or 2-stop bit generation
  • Internal baud generator
• Complete status reporting capabilities
• Line break generation and detection. Internal diagnostic capabilities:
  • Loop-back controls for communications link fault isolation
  • Break, parity, overrun, framing error simulation
• Full prioritized interrupt system controls
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus
• Fully synthesizable
• Static synchronous design and no internal tri-states