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D68000-CPU32

16/32-bit Microprocessor CPU32 (68020)

Description

D68000-CPU32 Soft Processor IP Core

The D68000-CPU32 is a high-performance, 32-bit soft CPU IP core that is fully binary-compatible with the industry-standard Motorola 68000 CPU32 architecture (MC68020 CPU32 variant). Designed for seamless reuse of legacy software, the core ensures full code compatibility with existing 68000/CPU32 toolchains and applications, making it ideal for industrial, automotive, and embedded SoC designs.

The D68000-CPU32 features a 16-bit data bus and a 24-bit address bus, delivering an optimal balance between performance and silicon efficiency. Its enhanced instruction set improves execution efficiency and throughput compared to the classic 68000 core, enabling faster program execution without software modification.

For efficient development and debugging, the core integrates a built-in DoCD-BDM debug interface, allowing real-time inspection, control, and system bring-up. The IP is delivered as a fully verified soft core, complete with an automated testbench and comprehensive regression test suite, supporting straightforward validation and integration at every stage of the SoC design and verification flow.

The D68000-CPU32 IP core is a proven solution for engineers seeking a 68000-compatible processor IP with improved performance, robust debug capabilities, and production-ready verification collateral.

DCD-SEMI D68000 Family – IP Core Comparison Table

Feature / IP Core D68000 D68000-CPU32 D68000-CPU32+
Architecture Compatibility Motorola 68000 Motorola CPU32 Motorola CPU32+ (MC68020-class)
Binary Compatibility 68000 software CPU32 software CPU32+ software
Data Bus Width 16-bit 32-bit 32-bit
Address Bus Width 24-bit 32-bit 32-bit
Instruction Set Classic 68000 Extended CPU32 Enhanced CPU32+
Execution Performance Baseline 68000 Higher than 68000 Highest in D68000 family
Target Use Case Pure 68000 legacy replacement CPU32 MCU migration High-performance CPU32+ systems
Debugger Interface DoCD-BDM (optional) DoCD-BDM Built-in DoCD-BDM
Software Recompilation Required ❌ No ❌ No ❌ No
FPGA / ASIC Ready ✅ Yes ✅ Yes ✅ Yes
Technology Independent ✅ Yes ✅ Yes ✅ Yes
Automated Testbench ✅ Yes ✅ Yes ✅ Yes
Verification Test Suite Complete Complete Complete
Typical Applications Industrial legacy control Automotive / industrial MCU Automotive ECUs, long-lifecycle SoCs
Best For Lowest-risk 68000 drop-in Balanced performance & compatibility Maximum performance with CPU32+ ISA

How to Choose

  • Choose D68000 if you need a pure 68000 replacement with minimal bus width and maximum legacy fidelity.

  • Choose D68000-CPU32 if your software targets CPU32 MCUs and needs higher performance with a 32-bit bus.

  • Choose D68000-CPU32+ if you want the fastest 68k-compatible core, extended instruction set, and built-in debug for modern FPGA/ASIC designs.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

Media

cpu32
Download full specification

D68000-CPU32 ASIC
D68000-CPU32 INTEL FPGA
D68000-CPU32 LATTICE
D68000-CPU32 MICROSEMI
D68000-CPU32 XILINX

Key features

  • Software compatible with industry standard 68000’s CPU32 (68020 version)
  • DoCD-BDM on-chip debugger as in CPU32
  • VBR register
  • Optimized shifts and rotations
  • Idle cycles removed to improve performance
  • Shorter effective address calculation time
  • Bus cycle timings identical to 68000
  • 32-bit data and address registers
  • 16 addressing modes:
    • Direct:
      • Data register direct – Dn
      • Address register direct – An
    • Indirect:
      • Register indirect – (An)
      • Post-increment register indirect – (An+)
      • Pre-decrement register indirect – (-An)
      • Register indirect with offset – (d16,An)
      • Indexed register indir. with offset – (d8,An,Xn)
      • Indexed register indir. with offset and base displacement – (bd,An,Xn)
    • PC relative:
      • with offset(d16,PC); with index and offset – (d8,PC,Xn)
      • with index offset and base displacement – (bd,PC,Xn)
    • Absolute data:
      • Absolute short (.W)
      • Absolute long (.L)
    • Immediate data:
      • Immediate – #data
      • Quick immediate – #n
    • Implied
  • 5 data types supported:
    • bits, BCD
    • bytes, words and long words
  • Arithmetic Logic Unit includes:
    • 8,16,32-bit arithmetic & logical operations
    • 16×16, 32×32 bit signed and unsigned multiplication
    • 32/16, 32/32, 64/32 bit signed and unsigned division
    • Boolean operations
  • Interrupt controller:
    • 7 priority levels interrupt controller
    • Unlimited number of virtual interrupt sources
    • Vectored and auto-vectored modes
    • Format $0, $2, $C exceptions support as in CPU32
  • Memory interface includes:
    • Up to 16 MB of address space
    • 16-bit data bus
    • Asynchronous bus control
  • M6800 family synchronous interface
  • 3- and 2- wire bus arbitration
  • Supervisor and user modes
  • Fully synthesizable, static synchronous design with no internal tri-states

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