D68000-CPU32+

D68000-CPU32+ – CPU32+ Compatible 32-bit 68000 Soft Core

The D68000-CPU32+ is a high-performance 32-bit soft processor IP core, fully binary compatible with the industry-standard Motorola 68000 CPU32+ architecture. Designed as a drop-in replacement for legacy 68k-based systems, it enables seamless migration of existing software to modern FPGA and ASIC platforms without recompilation.

Fully code-compatible with the CPU32+ version of the MC68020, the D68000-CPU32+ preserves the original programming model while delivering improved performance through an enhanced instruction set compared to the classic 68000 core.

Key Features

• CPU32+ / 68000 binary compatibility

• 32-bit data bus and 32-bit address bus

• Enhanced instruction set for higher execution performance

• Built-in DoCD-BDM debugger interface

• Deterministic, MCU-style execution model

• Ideal for long-lifecycle and legacy system support

Designed for Legacy Migration and Longevity

The D68000-CPU32+ IP core is optimized for projects that require long-term software stability, such as industrial, automotive, aerospace, and transportation systems built originally around 68000 or CPU32+ microcontrollers.

By maintaining strict binary compatibility, existing firmware, operating systems, and real-time applications can be reused without modification, significantly reducing migration risk, development cost, and time-to-market.

Integrated Debug and Verification Ready

For efficient development and system bring-up, the core integrates a DoCD-BDM (Background Debug Mode) debugger interface, enabling non-intrusive debugging and full CPU visibility during operation.

To accelerate SoC integration and validation, the D68000-CPU32+ is delivered with a fully automated testbench and a comprehensive regression test suite, supporting straightforward verification at every stage of the design flow.

Technology-Independent Soft Core

As a technology-independent soft IP, the D68000-CPU32+ can be implemented across a wide range of FPGA and ASIC process technologies, making it a future-proof solution for maintaining and extending legacy 68k-based designs.

Typical Applications

• Legacy 68000 / CPU32+ system replacement

• Industrial controllers and PLCs

• Automotive ECUs and body electronics

• Transportation and infrastructure systems

• Long-lifecycle embedded platforms

DCD-SEMI D68000 Family – IP Core Comparison Table

How to Choose

• Choose D68000 if you need a pure 68000 replacement with minimal bus width and maximum legacy fidelity.

• Choose D68000-CPU32 if your software targets CPU32 MCUs and needs higher performance with a 32-bit bus.

• Choose D68000-CPU32+ if you want the fastest 68k-compatible core, extended instruction set, and built-in debug for modern FPGA/ASIC designs.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with industry standard 68000’s CPU32+ (68020 version)
  
• DoCD-BDM on-chip debugger as in CPU32+
• VBR register
• 32-bit data and address registers
• 16 addressing modes:
  • Direct:
    • Data register direct – Dn
    • Address register direct – An
  • Indirect:
    • Register indirect – (An)
    • Post-increment register indirect – (An+)
    • Pre-decrement register indirect – (-An)
    • Register indirect with offset – (d16,An)
    • Indexed register indir. with offset – (d8,An,Xn)
    • Indexed register indir. with offset and base displacement – (bd,An,Xn)
  • PC relative:
    • with offset(d16,PC); with index and offset – (d8,PC,Xn)
    • with index offset and base displacement – (bd,PC,Xn)
  • Absolute data:
    • Absolute short (.W)
    • Absolute long (.L)
  • Immediate data:
    • Immediate – #data
    • Quick immediate – #n
  • Implied
• 5 data types supported:
  • bits, BCD
  • bytes, words and long words
• Arithmetic Logic Unit includes:
  • 8,16,32-bit arithmetic & logical operations
  • 16×16, 32×32 bit signed and unsigned multiplication
  • 32/16, 32/32, 64/32 bit signed and unsigned division
  • Boolean operations
• Interrupt controller:
  • 7 priority levels interrupt controller
  • Unlimited number of virtual interrupt sources
  • Vectored and auto-vectored modes
  • Format $0, $2, $C exceptions support as in CPU32+
• Memory interface includes:
  • Up to 4 GB of address space
  • 32-bit data bus
  • Asynchronous bus control
• M6800 family synchronous interface
• 3- and 2- wire bus arbitration
• Supervisor and user modes
• Fully synthesizable, static synchronous design with no internal tri-states