Configurable CAN Bus Controller with Flexible Data-Rate
DCAN FD bridge to APB, AHB, and AXI bus, it is a standalone controller for the Controller Area Network (CAN), widely used in automotive and industrial applications. The DCAN FD was designed in accordance with ISO 11898-1:2015 and conforms to:
- Bosch CAN 2.0B specification (2.0B Active) and
- CAN FD (flexible data-rate).
Sophisticated error detection functions (which increase communication reliability) and unique fault confinement (which guarantees network-wide data consistency) has decided CAN’s popularity. Because of its fundamental role in all aspects of security and safety, trustworthy implementations are crucial. That’s why DCD-SEMI developed a unique IP Core, which delimits the highest quality standards. The improved protocol overcomes standard CAN limits: data can be transmitted faster than with 1 Mbit/s and the payload (data field) is up to 64 bytes long and limited to 8 bytes anymore. When only one node is transmitting, the bit rate can be increased, because no nodes need to be synchronized. Of course, before the transmission of the ACK slot bit, the nodes need to be re-synchronized. The core has a simple CPU interface (8/16/32 bit configurable data width), with a small or big endian addressing scheme. Hardware message filtering (32 filters) and 128 bytes receive FIFO enable back-to-back message reception, with minimum CPU load. The DCAN FD is provided as HDL source code, allowing target use in FPGA and ASIC technologies.
Watch the DCAN FD presentation on DCD’s You Tube:
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Designed in accordance to ISO 11898-1:2015
- Supports CAN 2.0B and CAN FD frames
- Support up to 64 bytes data frames
- Flexible data-rates supported
- Supports emotas CANopen FD stack
- 8/16/32-bit CPU slave interface with small or big endianness
- Simple interface allows easy connection to CPU
- Supports both standard (11-bit identifier) and extended (29 bit identifier) frames
- Data rate up to 8 Mbps
- Hardware message filtering (dual/single filter) – up to 32 filters
- 128 byte receive FIFO and transmit buffer
- Overload frame is generated on FIFO overflow
- Normal & Listen Only Mode
- Transceiver Delay Compensation up to three data bit long
- Single Shot transmission
- Ability to abort transmission
- Readable error counters
- Last Error Code
- Fully synthesizable
- Static synchronous design with positive edge clocking and synchronous reset
- No internal tri-states
- Scan test ready
- Available system interface wrappers:
- AMBA – APB / AHB / AXI Lite Bus
- Altera Avalon Bus
- Xilinx OPB Bus
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