DFPIC165X

The DFPIC165X is a low-cost, high-performance, 8-bit, fully static soft IP Core, dedicated to operating with fast memory (typically on-chip). The core is designed with a special concern for low power consumption. The DFPIC165X is the software compatible with PIC16C54, PIC16C55, PIC16C56, PIC16C57, and PIC16C58 industry standards. It contains modified RISC architecture (2 times faster than the original implementation). The DFPIC165X has enhanced core features and a configurable hardware stack. Separate instruction and data buses allow a 12-bit wide instruction word, with a separate 8 -bit wide data. The DFPIC165X typically achieves a 2:1 code compression and an 8:1 speed improvement over other 8-bit microcontrollers in its class. The Core has 24 I/O lines and an 8-bit timer/counter with an 8-bit programmable Prescaler. The power-down SLEEP mode allows users to reduce power consumption. The user can wake the controller up from the SLEEP mode through a user reset or a watchdog overflow. An integrated Watchdog Timer with its own clock signal provides protection against software lock-up. The DFPIC165X Microcontroller fits well in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices, and telecom processors. Built-in power save mode and a small used area in programmable devices, make this IP perfect for applications with space and power consumption limitations. The DFPIC165X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow.

Each of DCD’s PIC Cores has a built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, user defined peripherals, data and program memories.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.

• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with industry standard PIC16C5X
• Harvard RISC architecture
• 2 times faster, compared to original implementation
• 33 instructions
• 12 bit wide instruction word
• Up to 256 bytes of internal Data Memory
• Up to 4K bytes of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available