Description

The DFPIC1655X is a low-costhigh performance, 8-bit, fully static soft IP Core, intended to operate with fast memory. The core has been designed with a special concern about low power consumption in combination with high performance. DCD’s IP Core is software compatible with industry standard PIC 16XXX Microcontrollers. It has a modified RISC architecture (2 times faster than the original implementation). The DFPIC1655X incorporates enhanced core features, configurable hardware stack, and multiple internal and external interrupt sources. Separate instruction and data buses allow a 14-bit wide instruction word with separate 8-bit wide data. The power-down SLEEP mode allows you to significantly reduce power consumption and “wake up” the controller through several external and internal interrupts and resets. An integrated Watchdog Timer, with its own dedicated clock signal, provides a protection against software lock-up. The DFPIC1655X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode and small used area in programmable devices, make this IP core perfect for applications with space and power consumption limitations. The DFPIC1655X is delivered with fully automated test bench and complete set of tests, allowing easy package validation at each stage of SoC design flow.
Each of DCD’s PIC Cores has a built-in support for a proprietary Hardware Debug System called DoCD™. It is a real-time hardware debugger which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals, data and program memories.

Key features

  • Software compatible with industry standard PIC16C5X
  • Harvard RISC architecture
  • 2 times faster, compared to original implementation
  • 33 instructions
  • 12 bit wide instruction word
  • Up to 256 bytes of internal Data Memory
  • Up to 4K bytes of Program Memory
  • Configurable hardware stack
  • Power saving SLEEP mode
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Technology independent HDL Source Code
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
Design Architecture improvement Code space DATA space Program word Number of instructions I/O Ports Timers Watchdog Timer CCP1 USART SLEEP Mode DoCD TM Size (gates)
DRPIC166X 4 64k 32 kB 14 bit 35 32 3 1 1 6700
DRPIC1655X 4 64k 32 kB 14 bit 35 32 1 - - ---
DFPIC166X 2 64k 32 kB 14 bit 35 32 3 1 1 5800
DFPIC165X 2 2k 128 12 bit 33 24 1 - - 2700
DFPIC1655X 2 64k 32 kB 14 bit 35 16 1 - - 3900

Features

DoCD Debugger

Power of Innovation is our primary target. That’s why our R&D focuses on every IP Core detail. As a result of that anxiety, some unique solutions were born. One of them is the PIC on-Chip Debugger (DoCD™), which is a complete debugging system dedicated for DCD’s DFPIC16XXX/DRPIC16XXX Microcontroller Cores.

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DoCD Debugger

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