DFSPI bridge to APB, AHB, AXI bus, it is a fully configurable SINGLE, DUAL, QUAD, and OCTAL SPI master/slave device, which allows the user to configure polarity and phase of the serial clock signal SCK. As an option, the DFSPI controller has built-in support for HyperBusTM specification and xSPI (Expanded Serial Peripheral Interface – JESD251A) specification. The SPI Controller allows easy communication with the most available SPI FLASH memories. The DFSPI fully supports NOR & NAND Flash Memory.

A serial clock line (SCK) synchronizes the shifting and sampling of the information on the serial data lines. It is a technology-independent design that can be implemented in various process technologies. The DFSPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate the most available synchronous serial peripheral devices.

The DFSPI can automatically drive selected by SSCR (Slave Select Control Register) slave select outputs (SS3O – SS0O), and address SPI slave device to exchange serially shifted data. It supports two DMA modes: single transfer and multi-transfer. These modes allow DFSPI to interface with higher-performance DMA units, which can interleave their transfers between CPU cycles or execute multiple byte transfers. DFSPI is fully customizable, delivering it in the exact configuration that meets users’ requirements.


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Key features

  • NOR & NAND Flash Memory Support
  • Set of software-accessible control registers to execute any Flash memory command
  • Supports any device clock frequency, polarity, and phase,
  • Programmable baud rate generator,
  • Built-in FLASH Commands decoder supports most popular FLASH devices,
  • Optional built-in AES Encoder/Decoder
  • DMA support
  • Optional support for various SPI Bus Standards: HyperBusTM, xSPI
  • Compliant with AMBA2 Specification, support APB, AHB, AXI bus interfaces
  • Single, Dual, Quad and OCTAL SPI transfer/reception
  • Execute in place – XIP functionality support
  • Data Bus Size configuration to 8, 16, or 32 bits wide
  • Optional FIFO size extension
  • Maximum supported Flash address range – 32 bits
  • Up to 4 SPI slaves can be addressed
    • Software Slave Select Output – SSO – selection
    • Automatic Slave Select outputs assertion
  • System error detection
  • Interrupt generation
  • Bit rates are generated as 1/ 2.. 1/255 of the system clock.
  • Four SPI transfer formats supported: CPOL/CPHA.
  • A simple interface allows easy connection to microcontrollers
  • Fully synthesizable, static synchronous design with no internal tri-states

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