DFSPI

DFSPI – Advanced SPI Master Controller & Bridge to APB, AHB, and AXI

The DFSPI IP Core from DCD-SEMI is a high-performance, fully configurable SPI master controller designed to seamlessly bridge SPI with AMBA APB, AHB, and AXI buses. Supporting Single, Dual, Quad, and Octal SPI modes, DFSPI enables fast, flexible, and reliable communication with modern serial memories and peripheral devices.

Engineered for next-generation embedded systems, it provides full configurability of serial clock polarity and phase (SCK), ensuring compatibility with virtually any SPI-based device available on the market.

HyperBus™ & xSPI (JESD251A) Ready

As an option, the DFSPI controller integrates native support for HyperBus™ and the xSPI (Expanded SPI – JESD251A) specification. This makes it an ideal choice for advanced SoCs and MCUs that require high bandwidth, low latency, and compatibility with the latest non-volatile memory standards.

Optimized for SPI Flash — NOR & NAND
DFSPI is designed for seamless communication with the most popular SPI Flash memories, including: NOR Flash, NAND Flash, Octal SPI Flash, and optionally HyperFlash® / HyperRAM®. Its architecture ensures high-speed data transfers, low power consumption, and reliable data integrity for embedded, automotive, and industrial applications.

Flexible, Technology-Independent Architecture
This IP Core is a technology-agnostic, synthesizable design that can be implemented across various process technologies. Its flexibility allows direct interfacing with a wide range of standard SPI peripherals from multiple manufacturers—making it suitable for SoCs, microcontrollers, and FPGA-based systems.

A robust serial clock (SCK) mechanism synchronizes data shifting and sampling across the interface, supporting all standard SPI clocking modes for maximum device compatibility.

Intelligent Slave-Select Control & DMA Support
The DFSPI features automatic control over multiple slave select outputs (SS3O–SS0O) via the SSCR (Slave Select Control Register), enabling precise management of communication with multiple SPI slave devices without CPU overhead.

To support high-performance memory and peripheral operations, DFSPI includes:

• Single-transfer DMA mode

• Multi-transfer DMA mode

These modes enable efficient data handling, either interleaved with CPU activity or in batch transfers, maximizing overall system throughput.

Fully Customizable SPI Master Controller
Every DFSPI core is tailored to specific project requirements. As with all DCD-SEMI IP solutions, customers receive a configuration aligned with their exact performance, integration, and interface needs.

Every DFSPI core is tailored to project requirements. As with all DCD-SEMI IP solutions, customers receive a configuration that matches their exact performance, integration, and interface needs.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• NOR & NAND Flash Memory Support
• Set of software-accessible control registers to execute any Flash memory command
• Supports any device clock frequency, polarity, and phase,
• Programmable baud rate generator,
• Built-in FLASH Commands decoder supports most popular FLASH devices,
• Optional built-in AES Encoder/Decoder
• DMA support
• Optional support for various SPI Bus Standards: HyperBus^TM, xSPI
• Compliant with AMBA2 Specification, support APB, AHB, AXI bus interfaces
• Single, Dual, Quad and OCTAL SPI transfer/reception
• Execute in place – XIP functionality support
• Data Bus Size configuration to 8, 16, or 32 bits wide
• Optional FIFO size extension
• Maximum supported Flash address range – 32 bits
• Up to 4 SPI slaves can be addressed
  • Software Slave Select Output – SSO – selection
  • Automatic Slave Select outputs assertion
• System error detection
• Interrupt generation
• Bit rates are generated as 1/ 2.. 1/255 of the system clock.
• Four SPI transfer formats supported: CPOL/CPHA.
• A simple interface allows easy connection to microcontrollers
• Fully synthesizable, static synchronous design with no internal tri-states