DI2CM-FIFO bridge to APB, AHB, AXI bus, this core provides an interface between a microprocessor/microcontroller and I2C bus. It can work as:

  • a master transmitter or
  • master receiver

depending on a working mode determined by the microprocessor/microcontroller. The DI2CM-FIFO core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems, and high-speed transmission mode. Built-in timer allows operation from a wide range of clk frequencies. The DI2CM-FIFO is a technology independent design that can be implemented in variety of process technologies.

Key features

  • Conforms to v.6.0 of the I2C specification
  • Master operation
    • Master transmitter
    • Master receiver
  • Support for all transmission speeds
    • Standard (up to 100 kb/s)
    • Fast (up to 400 kb/s)
    • Fast Plus (up to 1 Mb/s)
    • High Speed (up to 3,4 Mb/s)
    • ULTRA-FAST (up to 5 Mb/s)
    • Configurable FIFO size up to 256 Bytes
    • Configurable SDA/SCL glitch filter
    • Software programmable SDA/SCL bus timings
  • Arbitration and clock synchronization
  • Support for multi-master systems
  • Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Interrupt generation
  • Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready

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