DI2S

DI2S bridge to APB, AHB, and AXI bus, it is a universal solution that provides an interface between a microprocessor and I²S, left/right justified modes, PCM, and TDM audio protocol codec. Thanks to the flexible configuration it can work as a receiver, or transmitter in master or slave mode, with configurable channel length or sample size. Additionally, a number of audio blocks can be adjusted according to specific project needs.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Configurable number of independent audio modules with their respective FIFO
• Configurable TX/RX mode of each audio module
• Configurable master/slave mode support of each audio module
• Flexible I2S, LSB/MSB (right/left) justified, DSP, TDM modes support
• Configurable sample size (8, 10, 16, 20, 24, 32 bit)
• Configurable number of samples per frame (1 to 16)
• Configurable FIFO depth
• Flexible FIFO threshold interrupt control
• FIFO Underrun/overrun interrupt
• Inter modules clock synchronization
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus