DI3CM-FIFO bridge to APB, AHB, AXI bus, the Core incorporates all features required by the latest MIPI I3C specification.

The I3C (Improved Inter Integrated Circuit) is the next generation from I2C. Keeping the best assets from its elder brother, the I3C has major improvements in use and power and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced to a controller or application processor.

Digital Core Design maintains backward compatibility, enabling smooth transition from I2C to I3C and simple implementation. The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors, to support growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration and supports low-power, high-speed and other critical features that are currently covered by I2C and SPI.


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Key features

  • Conforms to MIPI I3C v1.0 specifications
  • MIPI Manufacturer ID: 0x03B3
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
  • Legacy I2C messaging
  • I2C-like Single Data Rate messaging (SDR)
  • Master operation with FIFO:
    • Master transmitter
    • Master receiver
  • Supports flexible transmission speed modes:
    • FAST-PLUS (up to 1000 kb/s)
    • SDR (up to 12,5 Mb/s)
  • Configurable FIFO size up to 256 Bytes
  • Configurable SDA/SCL glitch filter
  • Software programmable SDA/SCL bus timings
  • Multi-master systems supported
  • Interrupt generation
  • Allows operation from a wide range of input clock frequencies (build-in 12-bit clock timer)
  • Configurable interface allows easy connection to standard bus interfaces: APB, AHB, 8051, 80251, others
  • Support for in-band interrupts
  • Support for I3C common command codes
  • Dynamic address assignment (DAA) support
  • Command queue support
  • Low power management support
  • Fully interoperable with third-party I3C master and slave solutions
  • Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset
  • Available system interface wrappers:
    • AMBA – APB / AHB / AXI Bus
    • Altera Avalon Bus
    • Xilinx OPB Bus

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