MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder brother, the I3C has major improvements in use and power, and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced with a controller or application processor.
DCD maintains backward compatibility, enabling a smooth transition from I2C to I3C and simple implementation. The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors, to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration, and supports low-power, high-speed, and other critical features that are currently covered by I2C and SPI.
ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.
- Altera / Intel,
- Xilinx / AMD,
- Microsemi / Microchip,
- SK Hynix
- Conforms to MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
- MIPI Manufacturer ID: 0x03B3
- Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
- Dynamic address assignment (DAA) support
- Legacy I2C messaging
- I2C-like Single Data Rate messaging (SDR)
- Master operation with FIFO:
- Supports flexible transmission speed modes:
FAST-PLUS (up to 1000 kb/s)
SDR (up to 12,5 Mb/s)
- Configurable DAT/DCT size up to 16 slots
- Configurable FIFO size
- Interrupt generation
- Support for In-Band Interrupts
- Support for Hot-Join
- Support for I3C Common Command Codes
- Fully interoperable with third-party slave solutions
- Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset
- Available system interface wrappers:
AMBA – APB / AHB / AXI Bus
Altera Avalon Bus
Xilinx OPB Bus
- Optional support for HDR modes
DI2CM-FIFO bridge to APB, AHB, AXI bus, this core provides an interface between a microprocessor/microcontroller and I2C bus. It...
Support for all transmission speeds
Scan test ready
APB, OPB, Avalon Bus available
DI2CS bridge to APB, AHB, AXI bus, provides an interface between a microprocessor/microcontroller and I2C bus. It can work...
static synchronous design
DI2CSB bridge to APB, AHB, and AXI bus, provides an interface between a passive target device e.g. memory, LCD display,...
conforms to the latest I2C spec
DI2CMS bridge to APB, AHB, and AXI bus, it is a two-wire, bi-directional serial bus, which provides a simple...
conforms to v.3.0 I2C specification
DI2CM bridge to APB, AHB, AXI bus, the core provides an interface between a microprocessor/microcontroller and I2C bus. It...
support for all transmission speeds
scan test ready
APB, OPB, Avalon Bus available
The I3C (Improved Inter-Integrated Circuit) is the successor of the I2C bus. Keeping the best assets from its elder...
MIPI I3C specifications with Host Controller Interface (HCI) v1.1 specification