DMAC

DMAC bridge to APB, AHB, AXI bus. Ethernet specification served as the basis for the 802.3 standard, which specifies the physical and lower software layers. Since its commercial release, Ethernet has retained a good degree of compatibility. Digital Core Design focuses on innovation but remembers standardization. That’s why our DMAC solution is a hardware implementation of a media access control protocol defined by the IEEE standard. Thanks to our IP Core, functionality in design has never been better before. The DMAC in cooperation with the external PHY device enables network functionality in design. It is able to transmit and receive Ethernet frames to and from the network. Half and full duplex modes are supported, as well as 10 and 100 Mbit/s speed. The Core can work with a wide range of processors: 8, 16, and 32-bit data bus, either little or big endian byte order format. The DMAC provides a static configuration of PHY IC. Please remember that our design is technology independent, and thus can be implemented in a variety of process technologies. This Core strictly conforms to the IEEE 802.3 standard.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Conforms to IEEE 802.3-2002 specification
• Configurable width CPU interface with little or big endianess:
  • 8-bit
  • 16-bit
  • 32-bit
• Simple interface allows easy connection to CPU
• Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
• Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
• Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
• Supports full and half duplex operation at 10 Mbps or 100 Mbps
• CRC-32 algorithm:
  • calculates the FCS nibble at a time
  • automatic FCS generation and checking
  • able to capture frames with CRC errors if required
• Dynamic PHY configuration by STA management interface
• Early receive and transmit interrupts to increase data throughput
• Programmable MAC address
• Promiscuous mode support
• Allows operation from a wide range of input bus clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Lite design, small gate count and fast operation
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus