DMAC

DMAC IP Core — IEEE 802.3 Ethernet MAC Bridge for Embedded Systems

High-Performance Ethernet MAC Bridge for APB, AHB, and AXI Buses

The DMAC IP Core from Digital Core Design (DCD-SEMI) is a hardware implementation of the IEEE 802.3 media access control (MAC) protocol, providing robust Ethernet connectivity for embedded systems, SoCs, and FPGA designs. Combining innovation with standardization, this IP Core ensures reliable network functionality when paired with an external PHY device, enabling seamless transmission and reception of Ethernet frames.

Key Features

• IEEE 802.3-compliant MAC protocol for standardized Ethernet communication

• Supports 10/100 Mbps speeds in half- and full-duplex modes

• Compatible with 8-, 16-, and 32-bit processors

• Supports both little-endian and big-endian byte formats

• Static PHY IC configuration for simplified integration

• Technology-independent design deployable across FPGA, ASIC, and SoC technologies

• Ideal for embedded systems, IoT devices, automotive networks, and industrial applications

Why Choose DCD-SEMI DMAC IP Core

• Seamlessly bridges APB, AHB, and AXI buses with Ethernet networks

• Fully compatible with a wide range of processor architectures

• Provides high-speed, reliable, and standards-compliant Ethernet connectivity

• Flexible integration into FPGA, ASIC, and SoC designs

• Supports full- and half-duplex communication at 10 or 100 Mbps

DCD-SEMI’s DMAC IP Core enables engineers to implement robust, high-performance Ethernet functionality in embedded and industrial designs while ensuring full IEEE 802.3 compliance.

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For technical specifications or custom configurations, contact info@dcd-semi.com

• Conforms to IEEE 802.3-2002 specification
• Configurable width CPU interface with little or big endianess:
  • 8-bit
  • 16-bit
  • 32-bit
• Simple interface allows easy connection to CPU
• Narrow address bus (4 bits) with indirect I/O interface for transmitted and received data dual port memories
• Supports 10BASE-T and 100BASE-TX/FX IEEE 802.3 compliant MII PHYs
• Media Independent Interface (MII) for connection to external 10/100 Mbps PHY transceivers
• Supports full and half duplex operation at 10 Mbps or 100 Mbps
• CRC-32 algorithm:
  • calculates the FCS nibble at a time
  • automatic FCS generation and checking
  • able to capture frames with CRC errors if required
• Dynamic PHY configuration by STA management interface
• Early receive and transmit interrupts to increase data throughput
• Programmable MAC address
• Promiscuous mode support
• Allows operation from a wide range of input bus clock frequencies
• Fully synthesizable
• Static synchronous design
• Positive edge clocking
• No internal tri-states
• Lite design, small gate count and fast operation
• Scan test ready
• Available system interface wrappers:
  • AMBA – APB / AHB / AXI Bus
  • Altera Avalon Bus
  • Xilinx OPB Bus