DRPIC1655X – Low-Power, High-Performance PIC16-Compatible 8-bit CPU IP Core

The DRPIC1655X is a low-cost, high-performance, fully static 8-bit soft microcontroller IP core, engineered for SoC designs requiring PIC16 software compatibility, low power consumption, and efficient silicon utilization.

Designed to operate with fast, dual-ported memory, the DRPIC1655X delivers an optimal price–performance–power balance, making it one of the most cost-effective PIC-compatible CPU IP cores available on the market. The core is software-compatible with industry-standard PIC16XXX microcontrollers, allowing reuse of existing firmware, development tools, and design expertise.

Software Compatibility with PIC16XXX Microcontrollers

DRPIC1655X is software-compatible with the PIC16 family, enabling:

• Reuse of existing PIC16 firmware and libraries

• Familiar programming model and instruction set

• Fast migration from discrete PIC MCUs to ASIC or FPGA-based SoCs

This compatibility significantly reduces development risk, time-to-market, and software requalification effort.

Enhanced Harvard Architecture for High-Speed Execution

The core implements an enhanced Harvard architecture, featuring:

• Separate instruction and data memories

• Independent address and data buses

• 14-bit program memory

• 8-bit dual-ported data memory

This architecture allows simultaneous instruction fetch and data access, enabling instruction execution and memory operations to occur in parallel.

Thanks to a multi-stage pipeline, the next instruction is fetched from program memory while the current instruction is executed using data from data memory — resulting in a performance improvement of up to 4× compared to standard PIC16 architectures.

Efficient Instruction Pipeline

• Most instructions execute in a single system clock cycle

• Instructions that directly modify the program counter
  (GOTO, CALL, RETURN) require one additional cycle due to pipeline refill

• Deterministic execution behavior suitable for real-time control systems

This predictable timing makes DRPIC1655X ideal for control-oriented and timing-sensitive applications.

Ultra-Low-Power Design with Power-Save Mode

DRPIC1655X has been designed with low power consumption as a primary goal:

• Fully static implementation

• Built-in power-save mode

• Excellent performance-per-watt characteristics

• Ideal for battery-powered and duty-cycled systems

These features make the core especially suitable for energy-constrained embedded applications.

SoC-Ready Verification and Non-Intrusive Debugging

The DRPIC1655X is delivered with a fully automated testbench and a complete regression test suite, enabling easy validation and fast integration at every stage of the SoC design flow.

Each DRPIC1655X core includes built-in support for DoCD™ (Digital Core Design on-Chip Debugger) — a proprietary real-time hardware debug system that provides full SoC visibility without disrupting application execution.

DoCD™ Debug Capabilities

• Run, halt, single-step, step-over, and instruction skipping

• Read/write access to all CPU registers and SFRs, including user-defined peripherals

• Full access to program and data memories

• True non-intrusive debugging of running applications

Key Benefits for Design Engineers

• PIC16XXX software-compatible CPU IP

• Up to 4× faster than standard PIC16 architectures

• Enhanced Harvard architecture with dual-ported data memory

• Fully static, ultra-low-power design

• Built-in power-save mode

• Deterministic instruction timing

• Fully synthesizable ASIC & FPGA-ready soft IP

• Non-intrusive SoC debugging via DoCD™

• Complete verification environment included

Target Applications

🚗 Automotive & Appliances

• Motor control systems

• Automotive actuators

• Appliance control electronics

🌐 Low-Power & Remote Devices

• Remote transmitters and receivers

• Wireless sensor nodes

• Battery-powered controllers

🖱️ Consumer & Embedded

• Pointing devices and HID controllers

• Telecom and communication processors

• Cost-sensitive embedded systems

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Software compatible with PIC16C55X industry standard
• Pipelined Harvard RISC architecture
  • 4 times faster, compared to original implementation
• 35 instructions
• 14-bit wide instruction word
• Up to 32 kB of internal Data Memory
• Up to 64K Words of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code
• 800 MHz virtual clock frequency in a 0.35u technological process
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available