DRPIC166X

The DRPIC166X is a low-cost, high-performance, 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip) dual-ported memory. The core was designed with a special concern about low power consumption, assuring the best power use, price, and performance combination available on the market. The DRPIC166X softcore is software-compatible with industry-standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The 14-bit program memory and 8-bit dual port data memory allow instruction fetch and data operations to occur simultaneously. The advantage of this architecture is that the instruction fetch and memory transfers can be overlapped by a multi-stage pipeline so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory. The DRPIC166X architecture is 4 times faster compared to the standard architecture. Most instructions are executed within 1 system clock period, except instructions that directly operate on the PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes an additional one clock cycle.
The DRPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices, and telecom processors. Built-in power save mode makes this IP core perfect for applications where the power consumption aspect is critical. The DRPIC166X is delivered with a fully automated test bench and a complete set of tests, allowing easy package validation at each stage of the SoC design flow. Each of DCD’s PIC Cores has built-in support for a Hardware Debug System called DoCD™ – a real-time hardware debugger, which provides debugging capability of a whole System-on-Chip (SoC). Unlike other on-chip debuggers, the DoCD™ provides non-intrusive debugging of a running application. It can halt, run, step into or skip an instruction, read/write any contents of the microcontroller, including all registers, and SFRs, including user-defined peripherals and data and program memories.

DESIGN FEATURES:

ALL DCD’S IP CORES ARE TECHNOLOGY INDEPENDENT WHICH MEANS THAT THEY ARE 100% COMPATIBLE WITH ALL FPGA & ASIC VENDORS E.G.

• Altera / Intel,
• Xilinx / AMD,
• Lattice,
• Microsemi / Microchip,
  and others.
• TSMC
• UMC
• SK Hynix
  and others.

• Software compatible with PIC16C6X industry standard
• Pipelined Harvard RISC architecture
  • 4 times faster, compared to original implementation
• 35 instructions
• 14 bit wide instruction word
• Up to 32 kB of internal Data Memory
• Up to 64 K Words of Program Memory
• Configurable hardware stack
• Power saving SLEEP mode
• Fully synthesizable
• Static synchronous design
• Positive edge clocking and no internal tri-states
• Scan test ready
• Technology independent HDL Source Code
• 800 MHz virtual clock frequency in a 0.35u technological process
• USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available