The DRPIC166X is a low-cost, high performance, 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip), dual ported memory. The core has been designed with a special concern about low power consumption, assuring the best power use, price and performance combination available on the IP cores market.
The DRPIC166X soft core is software-compatible with the industry standard PIC 16XXX Microcontrollers. It implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The advantage of this architecture, is that the instruction fetch and memory transfers can be overlapped, by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory. The DRPIC166X architecture is 4 times faster compared to standard architecture. Most instructions are executed within 1 system clock period, except the instructions which directly operate on PC (GOTO, CALL, RETURN) program counter. This situation requires the pipeline to be cleared and subsequently refilled. This operation takes additional one clock cycle.
The DRPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices and telecom processors. Built-in power save mode, makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC166X is delivered with fully automated testbenchcomplete set of tests and DoCDTM on-chip hardware debugger,  allowing easy package validation, at each stage of SoC design flow.

Each of the DCD’s PIC Core, has built-in support for the DCD Hardware Debug System, called DoCDTM. It is a real-time hardware debugger, which provides debugging capability of a whole System on Chip (SoC). Unlike other on-chip debuggers, the DoCDTM provides a non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller, including all registers, SFRs, including user defined peripherals and data and program memories.

Key features

  • Software compatible with PIC16C6X industry standard
  • Pipelined Harvard RISC architecture
    • 4 times faster, compared to original implementation
  • 35 instructions
  • 14 bit wide instruction word
  • Up to 32 kB of internal Data Memory
  • Up to 64 K Words of Program Memory
  • Configurable hardware stack
  • Power saving SLEEP mode
  • Fully synthesizable
  • Static synchronous design
  • Positive edge clocking and no internal tri-states
  • Scan test ready
  • Technology independent HDL Source Code
  • 800 MHz virtual clock frequency in a 0.35u technological process
  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
Design Architecture improvement Code space DATA space Program word Number of instructions I/O Ports Timers Watchdog Timer CCP1 USART SLEEP Mode DoCD TM Size (gates)
DRPIC166X 4 64k 32 kB 14 bit 35 32 3 1 1 6700
DRPIC1655X 4 64k 32 kB 14 bit 35 32 1 - - ---
DFPIC166X 2 64k 32 kB 14 bit 35 32 3 1 1 5800
DFPIC165X 2 2k 128 12 bit 33 24 1 - - 2700
DFPIC1655X 2 64k 32 kB 14 bit 35 16 1 - - 3900


DOCD Debugger

Power of Innovation is our primary target. That’s why our R&D focuses on every IP Core detail. As a result of that anxiety there have been some unique solutions born. On of them is the PIC on-Chip Debugger (DoCDTM), which is complete debugging system, dedicated for DCD’s DFPIC16XXX/DRPIC16XXX Microcontroller Cores.

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DOCD Debugger

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