DRV32IMZicsr

DRV32IMZicsr – 32-bit RISC-V CPU IP Core with M & Zicsr Extensions and External Debug support.

The Core belongs to the latest DCD’s DRVX Core Family, with:

• a five-stage pipeline,
• Harvard architecture
• flexible size of program and data memory together with their allocation in address space.

Our solution offers performance tailored to the project requirements, starting from:

• Dhrystone: up to 1,15 DMIPS/MHz
• Coremark: up to 2,36 CoreMark/MHz
• Area utilization: from 14k gates

The DRV32IMZicsr is a high-performance 32-bit RISC-V CPU IP core implementing the RV32IM base architecture with M (Multiply/Divide) and Zicsr (Control and Status Registers) extensions, complemented by external debug support via JTAG. As a member of DCD-SEMI’s latest DRVX RISC-V Core Family, the core is engineered for scalable, safety-critical, and long-lifecycle SoC designs.

Designed with a five-stage pipeline and Harvard architecture, the DRV32IMZicsr delivers efficient instruction throughput, deterministic latency, and predictable real-time behavior. Flexible program and data memory sizing, along with configurable address space allocation, allows seamless adaptation to application-specific FPGA and ASIC requirements.

Performance & Area Efficiency

Performance scales with configuration, delivering up to:

• 1.15 DMIPS/MHz (Dhrystone)

• 2.36 CoreMark/MHz

• Area utilization starting from ~14k gates

This balance of performance and silicon efficiency makes the DRV32IMZicsr ideal for cost-sensitive and performance-driven designs alike.

SoC Integration & Interfaces

For straightforward system integration, the core supports AXI, AHB, and Native bus interfaces, ensuring compatibility with a broad range of SoC architectures across FPGA and ASIC platforms. The design is technology-independent and compatible with all major silicon vendors.

RISC-V Compliance & Debug

The DRV32IMZicsr includes 32 general-purpose registers and supports arithmetic, logic, load/store operations, branches, and jumps.

• The M extension provides hardware-accelerated integer multiplication and division.

• The Zicsr extension enables full access to Control and Status Registers, supporting interrupts, exceptions, timers, and performance counters in compliance with the RISC-V Privileged Architecture Specification (v20211203).

External debug is implemented via JTAG, fully compliant with RISC-V Debug Specification 0.13.2 and 1.0.0, ensuring interoperability with standard, off-the-shelf RISC-V debugging tools.

Safety-Ready & Ecosystem Support

Developed as an ISO 26262 Safety Element out of Context (SEooC), the DRV32IMZicsr is suitable for long-term, safety-oriented product designs. It integrates seamlessly with DCD-SEMI’s peripheral IP ecosystem, including UART, SPI, I2C, CAN, and more—enabling rapid creation of complete embedded platforms.

Verification & Reliability

To minimize integration risk, the core is delivered with a fully automated testbench and a comprehensive regression test suite, supporting efficient validation throughout the entire SoC design and verification flow.

Typical Applications:

• Automotive
• Industrial Control
• IoT
• Embedded Systems
• Consumer Electronics

DCD-SEMI DRVX RISC-V CPU IP Core Family – Comparison Table

Quick Selection Guide

• DRV32I – Minimal RISC-V core for cost-sensitive control applications

• DRV32IM – Balanced performance for general embedded and industrial SoCs

• DRV32IMZicsr – Safety-ready, debug-enabled core for automotive and industrial systems

ALL DCD’S IP CORES ARE TECHNOLOGY AGNOSTIC, ENSURING 100% COMPATIBILITY WITH ALL FPGA AND ASIC VENDORS.

For further details, email info@dcd-semi.com.

• Five‐stage pipeline
• Harvard architecture
• RV32I Base RISC-V ISA
• M extension
• Zicsr extension
• External Debug support
• JTAG debug interface
• Conformance to the RISC-V Debug Specification 0.13.2 and 1.0.0
• Highly configurable, including:
  • Flexible memory size and allocation
• Interface selection: AXI, AHB, Native
• M privilege level support
• Interrupt and exception handling
• Performance counters and timer
• Wide range of supported peripherals, including:
  • I2C
  • SPI
  • UART
  • CAN
  • and more
    • Developed as ISO26262 Safety Element out of Context (SEooC)
    • Technology independent HDL Source Code